Re: [PATCH v4 3/3] arm64: dts: qcom: Add Vicharak Axon Mini

[Ajit Singh <blfizzyy@gmail.com>]

On Tue, Jun 16, 2026 at 02:10:44PM +0530, Konrad Dybcio wrote:
> On 6/12/26 6:16 AM, Ajit Singh wrote:
> > On Wed, Jun 10, 2026 at 02:58:19PM +0530, Konrad Dybcio wrote:
> >> On 6/7/26 1:36 PM, Ajit Singh wrote:
> >>> Add DTS for the Vicharak Axon Mini board based on the Qualcomm
> >>> QCS6490 SoC.
> >>>
> >>> This adds debug UART, eMMC, UFS, SDIO WLAN, USB 2.0 host, PCIe
> >>> support along with regulators.
> >>>
> >>> The UFS ICE block is kept disabled because enabling it currently causes
> >>> an SError during qcom_ice_create() on this board. UFS works without ICE.
> >>>
> >>> Signed-off-by: Ajit Singh <blfizzyy@gmail.com>
> >>> ---
> >>
> >> [...]
> >>
> >>> +		vreg_l12c_1p8: ldo12 {
> >>> +			regulator-name = "vreg_l12c_1p8";
> >>> +			regulator-min-microvolt = <1800000>;
> >>> +			regulator-max-microvolt = <2000000>;
> >>> +			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> >>> +
> >>> +			/*
> >>> +			 * VREG_L12C_1P8 supplies the Ampak WLAN/BT module
> >>> +			 * VDDIO and the external 32.768 kHz oscillator.
> >>> +			 */
> >>
> >> Sorry for the long review timelines on the previous patch, many of us
> >> were out for conferences..
> >>
> >> Is the oscillator used for that WLAN module? Would you ideally like to
> >> be able to turn it on/off?
> > 
> > yes, oscillator is used for WLAN modules. Oscillator is powered from the same
> > VREG_L12C rail as WLAN VDDIO, so there is no separate regulator control to put
> > in pwrseq. So I think this will work fine?
> 
> Probably? My point is that you marked it as always-on, so it will *never*
> turn off right now. For e.g. Qualcomm wifi, there's some timing spec that
> needs to be met wrt delays between toggling various regulators and GPIOs
> going to the module, hence I suggested you may need some pwrseq inbetween
> to achieve reliable powering on/off
> 
Right, I checked the module timing requirements.

The module requires VBAT to be present before or at the same time as VDDIO, and
WL_REG_ON to be asserted only after VBAT/VDDIO are valid, around 2 sleep-clock
cycles later.

On this board, VBAT is the shared VCC_3V3 rail and is enabled by hardware, so
it is already present before VDDIO. VREG_L12C supplies WLAN/BT VDDIO and is
kept on. The WL_REG_ON timing is handled by the existing mmc-pwrseq-simple
reset GPIO/delay before SDIO enumeration.

So I think the current sequencing matches the module timing requirement.

> Konrad

Ajit