From: Brian Masney <bmasney@redhat.com>
To: David Carlier <devnexen@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Xukai Wang <kingxukai@zohomail.com>,
Conor Dooley <conor.dooley@microchip.com>,
Troy Mitchell <TroyMitchell988@gmail.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: canaan: Clear rate fields before reprogramming dividers
Date: Thu, 18 Jun 2026 12:55:15 -0400 [thread overview]
Message-ID: <ajQi85kD1jVeqrQW@redhat.com> (raw)
In-Reply-To: <20260618045030.12581-1-devnexen@gmail.com>
On Thu, Jun 18, 2026 at 05:50:30AM +0100, David Carlier wrote:
> The rate set_rate helpers perform a read-modify-write on the divider
> and multiplier registers but only ever OR the new value in, without
> first masking off the existing field. The first write after reset lands
> on a zeroed field and looks correct, but any later reprogramming leaves
> the old bits set: the field becomes the bitwise OR of the previous and
> new encodings, corrupting the divider or multiplier.
>
> Mask off each field before writing the new value so reprogramming a
> clock to a different rate produces the intended register contents.
>
> Fixes: a7b7c7c6c016 ("clk: canaan: Add clock driver for Canaan K230")
> Signed-off-by: David Carlier <devnexen@gmail.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
prev parent reply other threads:[~2026-06-18 16:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-18 4:50 [PATCH] clk: canaan: Clear rate fields before reprogramming dividers David Carlier
2026-06-18 8:18 ` Xukai Wang
2026-06-18 16:55 ` Brian Masney [this message]
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