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Frank > controller. It defines the new register offsets and bitfield mappings > required for the A733, which slightly differs from the older `sun6i` > series. > > Changes: > - New register macros for A733 interrupt enable `DMA_IRQ_EN_A733` and > status `DMA_IRQ_STAT_A733`. > - New `SRC_HIGH_ADDR_32G` and `DST_HIGH_ADDR_32G` macro to handle the > 32G high-address field in the LLI. > - Implemented `sun6i_dma_set_addr_a733` and A733-specific interrupt > register accessors. > - Added `sun60i_a733_dma_config`, which ties all the refactored > functionality together for this specific hardware. > > Signed-off-by: Yuanshen Cao > --- > drivers/dma/sun6i-dma.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 87 insertions(+) > > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c > index 196a0d73b221..4808015934cc 100644 > --- a/drivers/dma/sun6i-dma.c > +++ b/drivers/dma/sun6i-dma.c > @@ -52,6 +52,15 @@ > #define SUNXI_H3_SECURE_REG 0x20 > #define SUNXI_H3_DMA_GATE 0x28 > #define SUNXI_H3_DMA_GATE_ENABLE 0x4 > + > +/* > + * sun60i specific registers > + */ > +#define DMA_IRQ_EN_A733(x) ((x) * 0x40 + 0x134) > +#define DMA_IRQ_STAT_A733(x) ((x) * 0x40 + 0x138) > + > +#define DMA_IRQ_CHAN_NR_A733 1 > + > /* > * Channels specific registers > */ > @@ -100,6 +109,8 @@ > */ > #define SRC_HIGH_ADDR(x) (((x) & 0x3U) << 16) > #define DST_HIGH_ADDR(x) (((x) & 0x3U) << 18) > +#define SRC_HIGH_ADDR_32G(x) (((x) & 0x7U) << 11) > +#define DST_HIGH_ADDR_32G(x) (((x) & 0x7U) << 15) > > /* > * Various hardware related defines > @@ -257,6 +268,23 @@ static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) > DMA_STAT, readl(sdev->base + DMA_STAT)); > } > > +static inline void sun6i_dma_dump_com_regs_a733(struct sun6i_dma_dev *sdev) > +{ > + int i; > + > + for (i = 0; i < sdev->num_pchans / sdev->cfg->num_channels_per_reg; i++) { > + dev_dbg(sdev->slave.dev, "Common register:\n" > + "chan num %d\n" > + "\tmask(%04x): 0x%08x\n" > + "\tpend(%04x): 0x%08x\n" > + "\tstats(%04x): 0x%08x\n", > + i, > + DMA_IRQ_EN_A733(i), readl(sdev->base + DMA_IRQ_EN_A733(i)), > + DMA_IRQ_STAT_A733(i), readl(sdev->base + DMA_IRQ_STAT_A733(i)), > + DMA_STAT, readl(sdev->base + DMA_STAT)); > + } > +} > + > static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev, > struct sun6i_pchan *pchan) > { > @@ -360,21 +388,41 @@ static u32 sun6i_read_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg) > return readl(sdev->base + DMA_IRQ_EN(irq_reg)); > } > > +static u32 sun6i_read_irq_en_a733(struct sun6i_dma_dev *sdev, u32 irq_reg) > +{ > + return readl(sdev->base + DMA_IRQ_EN_A733(irq_reg)); > +} > + > static void sun6i_write_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val) > { > writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); > } > > +static void sun6i_write_irq_en_a733(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val) > +{ > + writel(irq_val, sdev->base + DMA_IRQ_EN_A733(irq_reg)); > +} > + > static u32 sun6i_read_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg) > { > return readl(sdev->base + DMA_IRQ_STAT(irq_reg)); > } > > +static u32 sun6i_read_irq_stat_a733(struct sun6i_dma_dev *sdev, u32 irq_reg) > +{ > + return readl(sdev->base + DMA_IRQ_STAT_A733(irq_reg)); > +} > + > static void sun6i_write_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status) > { > writel(status, sdev->base + DMA_IRQ_STAT(irq_reg)); > } > > +static void sun6i_write_irq_stat_a733(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status) > +{ > + writel(status, sdev->base + DMA_IRQ_STAT_A733(irq_reg)); > +} > + > static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) > { > struct sun6i_desc *txd = pchan->desc; > @@ -695,6 +743,17 @@ static void sun6i_dma_set_addr_a100(struct sun6i_dma_dev *sdev, > DST_HIGH_ADDR(upper_32_bits(dst)); > } > > +static void sun6i_dma_set_addr_a733(struct sun6i_dma_dev *sdev, > + struct sun6i_dma_lli *v_lli, > + dma_addr_t src, dma_addr_t dst) > +{ > + v_lli->src = lower_32_bits(src); > + v_lli->dst = lower_32_bits(dst); > + > + v_lli->para |= SRC_HIGH_ADDR_32G(upper_32_bits(src)) | > + DST_HIGH_ADDR_32G(upper_32_bits(dst)); > +} > + > static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev, > struct sun6i_dma_lli *v_lli, > dma_addr_t src, dma_addr_t dst) > @@ -1339,6 +1398,33 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { > SUN6I_DMA_IRQ_A31_COMMON_OPS > }; > > +/* > + * The A733 binding uses the number of dma channels from the > + * device tree node. > + */ > +static struct sun6i_dma_config sun60i_a733_dma_cfg = { > + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, > + .set_burst_length = sun6i_set_burst_length_h3, > + .set_drq = sun6i_set_drq_h6, > + .set_mode = sun6i_set_mode_h6, > + .set_addr = sun6i_dma_set_addr_a733, > + .dump_com_regs = sun6i_dma_dump_com_regs_a733, > + .read_irq_en = sun6i_read_irq_en_a733, > + .write_irq_en = sun6i_write_irq_en_a733, > + .read_irq_stat = sun6i_read_irq_stat_a733, > + .write_irq_stat = sun6i_write_irq_stat_a733, > + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), > + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), > + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | > + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | > + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), > + .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | > + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | > + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), > + .num_channels_per_reg = DMA_IRQ_CHAN_NR_A733, > + .has_mbus_clk = true, > +}; > + > /* > * The V3s have only 8 physical channels, a maximum DRQ port id of 23, > * and a total of 24 usable source and destination endpoints. > @@ -1375,6 +1461,7 @@ static const struct of_device_id sun6i_dma_match[] = { > { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, > { .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg }, > { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg }, > + { .compatible = "allwinner,sun60i-a733-dma", .data = &sun60i_a733_dma_cfg }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(of, sun6i_dma_match); > > -- > 2.54.0 >