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Mon, 22 Jun 2026 13:51:26 -0700 Date: Mon, 22 Jun 2026 13:51:24 -0700 From: Nicolin Chen To: Breno Leitao CC: Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , , , , , , Subject: Re: [PATCH] iommu/arm-smmu-v3: Disable PRI when no priq IRQ is available Message-ID: References: <20260622-smmu_pri-v1-1-14ad92b6043f@debian.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260622-smmu_pri-v1-1-14ad92b6043f@debian.org> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A105:EE_|BY5PR12MB4195:EE_ X-MS-Office365-Filtering-Correlation-Id: a86c933d-63a8-4cfb-ba1e-08ded0a01401 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|7416014|36860700016|1800799024|82310400026|18002099003|22082099003|13003099007|11063799006|5023799004|56012099006; X-Microsoft-Antispam-Message-Info: Gf3jU11BG7BkxWhWUm0PXxsGtSMXcBa8fK5VwwxMjzdiy/mQ+Ng3zJbHwtUXpf770hMVTF3n55Mdfm1RZSxULqkNfKY83zo804HEEYpbdfI9OA3lKbPzzJp6wVUAvMpVjSvh1LF9Vh06tXiXuuMBZyTwoBxIP+PlehbaTjNSVd0TzsQG2oXT6Wqd6iAxLzToBOQqndj7b1tXjUlHPbJUJLjYjruFfo8gBsaSHcrIsTtSmKayCA2uNiAy1UGtBDKsxJIRIzFMDUKg5v4DyjckyQBH9q6JwORZnEA4xU1SHz0IBhZ6gR78RkqsG+boOK6qJ0W6/UXiRHqkjb9zbqFGp1kRF0LgWnT8mZ91SzitsNyZIORIBU142vnOGXB7quWV6OZJ0tg6/NQd0SGbjU9Q3dwYCehOb0ZHVp66EfTTGtttyD0pc+0tIh7FNQvME+67cULEUqGc41lFIaofAERweKA5QnMZz9JPaUpkPnUbYqsogxW3aLpgvYI1LDsuPuGGw5fgJkpBtWn5Dw5Ee6241yzQKcG3mvwi6tGaN/YUioRm7N2Jy0RsTKfFIbBPsJ4X6mpFCA0Mk5dTcVoI1KQNLZMK1gs6hVJh4iK5RqZkA3dSuUh1ZqYS1HfXGTmlbhtyFtcur5RQuIDG+s0LrdimgFqxM4hxS34cZy+/EVQbTJy3edGs8s7a0ZVvaA7sfsCIZwCflfnpai5izexgQCcz2w== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(23010399003)(7416014)(36860700016)(1800799024)(82310400026)(18002099003)(22082099003)(13003099007)(11063799006)(5023799004)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Aj3W2Uo7pDm6kGHTcRYlSWmWTwFlDjZUl+lvasTlCCjTKq1ssbCyO3P1M1luoe8lGQL3NGB3jFfjQShx4DSjTieQ6F7l2zvycIlt80mrYZCBZeqmGAtjvhrp2mBhoCayoC61jTm5NNWGSXUe7n0dCKEUvBWar6nWivKHzgdD8+l6cucGmRRW1qAczaxVcsih2/b67vAXWyTRykBWHTVb/GWA3O5XxafO11XHLYu2KCzxIEeiOKq2kYAkJz+svtVwWfIMn56yh6/hlHgaFQQU/w9XZgCV1Vc6ggkR+5+k8kZslRWpziBhJsDCfjHKWrFJc5aKAn3ehWpf7e0OtX0Z921S9f3URr9CxrLYQhKjK/vqTPx8ZZKMsLu6Xto7YBiz7vhZLQNjNk75LfG77YskyGpPod7OujIbahbrukvOaXiGTqNF1amofh4MkDQTQDCA X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2026 20:51:48.0799 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a86c933d-63a8-4cfb-ba1e-08ded0a01401 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A105.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4195 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260622_135213_930651_E09B2ACB X-CRM114-Status: GOOD ( 17.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 22, 2026 at 09:17:03AM -0700, Breno Leitao wrote: > When platform firmware advertises an SMMU as PRI-capable in IDR0.PRI > but does not assign a GSIV for its priq, arm_smmu_setup_unique_irqs() > warns and continues. ARM_SMMU_FEAT_PRI remains set, so the driver > still allocates the PRI queue, programs PRIQ_BASE/PROD/CONS, enables > IRQ_CTRL_PRIQ_IRQEN, and lets IOMMU_DEV_FEAT_IOPF be advertised to > upper layers. Page Request messages from devices land in a queue no > one drains, and SVA binds appear to succeed while silently dropping > every page fault. > > Clear ARM_SMMU_FEAT_PRI in the missing-IRQ path so every PRI-gated > site in the driver consistently treats the SMMU as PRI-less, instead of > the half-baked stated. > > Signed-off-by: Breno Leitao > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index a10affb483a4f..44bafbb38e242 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -4659,7 +4659,8 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) > dev_warn(smmu->dev, > "failed to enable priq irq\n"); > } else { > - dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); > + dev_warn(smmu->dev, "no priq irq - disabling PRI\n"); > + smmu->features &= ~ARM_SMMU_FEAT_PRI; This is covered by PATCH-7 in my PRI series: https://lore.kernel.org/linux-iommu/cover.1779944354.git.nicolinc@nvidia.com/ FWIW, changing arm_smmu_setup_unique_irqs() alone isn't complete, as Sashiko pointed it out: https://sashiko.dev/#/patchset/20260622-smmu_pri-v1-1-14ad92b6043f%40debian.org Nicolin