From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 716513D5679 for ; Tue, 23 Jun 2026 14:58:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782226726; cv=none; b=M0S2Y+BEGrueo2MwDQLWNmb2Hte83+InR3qo96Dt4QWcOgPpsbfh3o/JVoQ1K8YbciT9IYusPui3L4iC91CslMCKzbvppHIL316M+AyNfmz0Nz5AQgH/LKDYxEH8qVXlXYUuAdYyQlZ7TOrk1sxjEbg9Ixx4c0b6UBWq8YCUgBE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782226726; c=relaxed/simple; bh=WiANHJqy7C9nAbf9+8IkS3SwkNgIILh9FcPzXJ3mOaQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=CyEEPiCdXO3eoxpivrriG7UBG6CGrsGoPkzMjNuwDIqrfnj4iYq4ylpLBk5LZpmDQM/MvAoLYQjaxVWqNL3GEhcHPI0WuqB0/r7Gd+etjT98EqqwgJ4yYPKrQlEwu1jxXJB9Ux5NLiqabkE7AeoQDfow5Fn6OuJtF6srzwL3tKc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Be7l3Ehv; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Be7l3Ehv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782226726; x=1813762726; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=WiANHJqy7C9nAbf9+8IkS3SwkNgIILh9FcPzXJ3mOaQ=; b=Be7l3EhvYDoWmMaXWr8wP+LwVo5DOh4EfeozQyf96x6cV8bB8uYivi+i swlfiiF117q0T9L8TMTaZ8eQAKXiIhjMxiGXN6wuE+qouj8OtJom5APsC JYuyYtzlWJvJDnzeuSvkWvwV5O4JuxVjpL5FT4MHTTDR6B0JXRNlNUX51 0nzOHFJVu1ibT4u0b4zmnsPw6AXPQjeGhkQO32fXjJlMloeqjovZMeQuB lIHxaCoSzAsp+9O0BNoOONUUklBC/83zqilqNuWmJtqYqvjn5Ap1uyEo4 5Cu5SpP8z43txIQZnq6vAmv53RYNHCuFPVicUyzohO0d/BSSLodNpLZeR g==; X-CSE-ConnectionGUID: JugIIC/aR7mtt5K2GmsZaQ== X-CSE-MsgGUID: IEhYOn+NQhydvCVPvPMOGQ== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="83013018" X-IronPort-AV: E=Sophos;i="6.24,220,1774335600"; d="scan'208";a="83013018" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 07:58:45 -0700 X-CSE-ConnectionGUID: vfQPwAw4SQ2L/E7gp7BeCA== X-CSE-MsgGUID: NU78riF4SE6yDCuVAFooig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,220,1774335600"; d="scan'208";a="253899854" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa004.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 07:58:42 -0700 Date: Tue, 23 Jun 2026 16:58:39 +0200 From: Raag Jadav To: Andy Shevchenko Cc: Heikki Krogerus , Rodrigo Vivi , Matthew Brost , Thomas =?iso-8859-1?Q?Hellstr=F6m?= , "Michael J . Ruhl" , Mika Westerberg , Riana Tauro , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 2/2] drm/xe/mcu_i2c: Take over control of the controller enabling Message-ID: References: <20260622114759.3464047-1-heikki.krogerus@linux.intel.com> <20260622114759.3464047-3-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jun 23, 2026 at 01:56:53PM +0300, Andy Shevchenko wrote: > On Mon, Jun 22, 2026 at 01:47:59PM +0200, Heikki Krogerus wrote: > > Some platforms make an assumption that the i2c controller's > > enabled state indicates also the power state of the > > controller. This can create a problem when the controller is > > in disabled state, because the hardware may assume > > incorrectly that it is then also in low-power state. > > > > To fix this, the controller is kept enabled by taking over > > the IC_ENABLE register. The controller has to be disabled > > when the configuration is updated and when the target > > address or the slave address are assigned, so disabling it > > when IC_CON, IC_TAR or IC_SAR registers are programmed, and > > then re-enabling it again. > > ... > > > +#define IC_CON 0x00 > > +#define IC_TAR 0x04 > > +#define IC_SAR 0x08 > > +#define IC_ENABLE 0x6c > > +#define IC_ENABLE_STATUS 0x9c > > Heh, I would like to have a shared header with the registers, but dunno > if the prons will weight out the cons. Perhaps something like i2c-algo-pca.h? Raag