From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02CC4396D15 for ; Wed, 24 Jun 2026 10:14:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782296043; cv=none; b=sDkDWhdPrstsfaGPvjTlO9dpIrlWsST64l8/upbLCUmR1fYc6dW42BJEdExhHaatxOEPWGw12rKf9Avd1A22gWY/rgNhaw8euKinV/JPVG9kY6nxuswL6qrSe7hzdwQV9BOAgM65IIIBPc1zau4kHdivoHZg+v8xgxMRuV/dGcM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782296043; c=relaxed/simple; bh=qdlq6hba7pUusRaImB9v9jjJNCh0CdFKio3R9kCkqvU=; h=Date:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To:From; b=e1Pu0m1PX6R9wijZgv+LSQ1JJWZphpd20Jln/EMh99Aj0XopzSZBmR8+9eWZzU4rgg9/HvcR14a/5Q6l7K0Sp9RWJ/cD5JzIQ39llbhS55ZlhlbGRlIUPgPrMq5CY8E6/zlWxtVZygzWlVXWBlJaKWEyr27CpsIUavZsuCDxWR0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cb1UhANJ; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cb1UhANJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782296042; x=1813832042; h=date:to:cc:subject:message-id:references:mime-version: in-reply-to:from; bh=qdlq6hba7pUusRaImB9v9jjJNCh0CdFKio3R9kCkqvU=; b=cb1UhANJD1yCWt32cfuhO2bQVFbxQk0b1yQ2QrsJZjPSQlo5XDM5Lp9b JVcPWxTgSSyUtxa2DgJaGOs37AvG1wfLB7cPz0CGHpY2UJ6v+/7QZdOgb gqfequiD/m/QRgHpAtpTm9FA8XBpg9nSgwxyD9ib46MHn5P6gwUFAIqPd D7yuneUwP93fGXnG05xghuZKRXQXYgxPFPtboEc2lc9NSmjGJeIBZK1KB 0eUk0UZsXFjaRbafPpnKRp6Q+lFGMC+q7B0RpHDDnfALVxqwFp0tLYliL h5bXvEAlKsx9dayai5dxBdjnZBRDBHaLrXDjv2psx0BvyWwMiPMD6hkSY A==; X-CSE-ConnectionGUID: l2J/i5zTTa+WAhc4DmXAGg== X-CSE-MsgGUID: 5zay2e7qS/+e9sv3pST8Ow== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="82925089" X-IronPort-AV: E=Sophos;i="6.24,222,1774335600"; d="scan'208";a="82925089" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 03:14:02 -0700 X-CSE-ConnectionGUID: bXmnm89bST2CeeccQjTeLg== X-CSE-MsgGUID: 924S/CsuRYC0LULGuH/zSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,222,1774335600"; d="scan'208";a="273873653" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa001.fm.intel.com with ESMTP; 24 Jun 2026 03:13:59 -0700 Received: by black.igk.intel.com (Postfix, from userid 1008) id B4CC395; Wed, 24 Jun 2026 12:13:57 +0200 (CEST) Date: Wed, 24 Jun 2026 13:13:56 +0300 To: Raag Jadav Cc: Rodrigo Vivi , Matthew Brost , Thomas =?iso-8859-1?Q?Hellstr=F6m?= , "Michael J . Ruhl" , Andy Shevchenko , Mika Westerberg , Riana Tauro , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 2/2] drm/xe/mcu_i2c: Take over control of the controller enabling Message-ID: References: <20260622114759.3464047-1-heikki.krogerus@linux.intel.com> <20260622114759.3464047-3-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: rom: Heikki Krogerus From: Heikki Krogerus On Tue, Jun 23, 2026 at 04:39:05PM +0200, Raag Jadav wrote: > On Mon, Jun 22, 2026 at 01:47:59PM +0200, Heikki Krogerus wrote: > > Some platforms make an assumption that the i2c controller's > > enabled state indicates also the power state of the > > controller. This can create a problem when the controller is > > in disabled state, because the hardware may assume > > incorrectly that it is then also in low-power state. > > > > To fix this, the controller is kept enabled by taking over > > the IC_ENABLE register. The controller has to be disabled > > when the configuration is updated and when the target > > address or the slave address are assigned, so disabling it > > when IC_CON, IC_TAR or IC_SAR registers are programmed, and > > then re-enabling it again. > > ... > > > static int xe_i2c_read(void *context, unsigned int reg, unsigned int *val) > > { > > struct xe_i2c *i2c = context; > > > > - *val = xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET)); > > + switch (reg) { > > Curious, should I expect DW_IC_INTR_MASK case here which skips the MMIO? Probable not. We have the ACCESS_POLLING flag set, so the i2c-designware will only write 0 to that register. Check __i2c_dw_write_intr_mask(). Thanks, -- heikki