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From: "Nuno Sá" <noname.nuno@gmail.com>
To: Andy Shevchenko <andriy.shevchenko@intel.com>
Cc: Frank Li <Frank.li@oss.nxp.com>,
	nuno.sa@analog.com,  dmaengine@vger.kernel.org,
	linux-iio@vger.kernel.org, Vinod Koul <vkoul@kernel.org>,
	 Frank Li <Frank.Li@kernel.org>,
	Lars-Peter Clausen <lars@metafoo.de>,
	 Jonathan Cameron <jic23@kernel.org>,
	David Lechner <dlechner@baylibre.com>,
	 Andy Shevchenko <andy@kernel.org>
Subject: Re: [PATCH RFC 2/3] dmaengine: dma-axi-dmac: Switch to bitmap-based address width masks
Date: Wed, 24 Jun 2026 16:33:53 +0100	[thread overview]
Message-ID: <ajv4NVSmSR_dn9CJ@nsa> (raw)
In-Reply-To: <ajpfmQ6JID5rHLMF@ashevche-desk.local>

On Tue, Jun 23, 2026 at 01:27:37PM +0300, Andy Shevchenko wrote:
> On Tue, Jun 23, 2026 at 11:14:51AM +0100, Nuno Sá wrote:
> > On Mon, Jun 22, 2026 at 01:34:39PM -0500, Frank Li wrote:
> > > On Mon, Jun 22, 2026 at 05:09:10PM +0100, Nuno Sá wrote:
> > > > On Mon, Jun 22, 2026 at 09:51:46AM -0500, Frank Li wrote:
> > > > > On Mon, Jun 22, 2026 at 10:26:41AM +0100, Nuno Sá wrote:
> 
> ...
> 
> > > If support 4Byte, it native supportted any N*4Byte.
> > > 
> > > So needn't bit mask to indicate all support bytes.
> > 
> > > > > each transfer, dma_slave_cfg should set specific bus width requirement.
> > > > >
> > > > > If memory have requirement for 32bytes, typical cache line length for
> > > > > hardwaer coherence transfer, it should use dmaengine_alignment.
> > > > >
> > > > > So I think only need set min value should be enough if fix pcm_dmaegine.c.
> > > >
> > > > What fix for pcm_dmaegine.c? Not sure there's anything to be fixed in
> > > > there... The code seems to use the dma bus width to match against PCM
> > > > formats supported and filter only the ones we can support (per dma cap).
> > > 
> > > if cap is one byte, it should support 8, 16, 24, 32, 64
> > > if cap is two byte, it should support 16, 32, 64
> > > if cap is 4 byte,  it only support 32 and 64.
> > 
> > Well, Now I see your point but not exactly. Because we do have
> > 
> > DMA_SLAVE_BUSWIDTH_3_BYTES
> > 
> > and it might be used by the pcm_dmaengine code,
> > 
> > There are also some controllers that set it. But it looks like all that
> > set it also set 1byte.
> 
> But this might be not true for all HW in the world. In previous reply I made
> a comparison with MMIO accesses where not all HW that needs 1-byte read can
> cope with that. If there is some proof that this is the case when 1-byte
> DMA bus implies 3-bytes (or other odd number), I would like to see it.

True. I'm also not too keen in making the above assumption and have no
proof that it will work for the controllers we support.

- Nuno Sá

> 
> > So your suggestion might still hold and work but I'm not too convinced
> > that having the array complicates things that bad when compared with the
> > risk of breaking existing code.
> 
> > > Needn't mask each bit.
> 
> -- 
> With Best Regards,
> Andy Shevchenko
> 
> 

  parent reply	other threads:[~2026-06-24 15:32 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-16 15:40 [PATCH RFC 0/3] dmaengine: Support address bus widths of 32 bytes and above Nuno Sá
2026-06-16 15:40 ` Nuno Sá via B4 Relay
2026-06-16 15:40 ` [PATCH RFC 1/3] " Nuno Sá
2026-06-16 15:40   ` Nuno Sá via B4 Relay
2026-06-16 15:55   ` sashiko-bot
2026-06-16 16:19   ` Frank Li
2026-06-18 17:13     ` Nuno Sá
2026-06-18 18:08       ` Frank Li
2026-06-16 15:40 ` [PATCH RFC 2/3] dmaengine: dma-axi-dmac: Switch to bitmap-based address width masks Nuno Sá
2026-06-16 15:40   ` Nuno Sá via B4 Relay
2026-06-16 15:52   ` sashiko-bot
2026-06-16 16:23   ` Frank Li
2026-06-18 17:10     ` Nuno Sá
2026-06-19 16:22       ` Frank Li
2026-06-19 19:02         ` Frank Li
2026-06-22  9:26           ` Nuno Sá
2026-06-22 14:51             ` Frank Li
2026-06-22 16:09               ` Nuno Sá
2026-06-22 18:34                 ` Frank Li
2026-06-23  9:50                   ` Andy Shevchenko
2026-06-23 13:28                     ` Frank Li
2026-06-23 15:01                       ` Andy Shevchenko
2026-06-23 10:14                   ` Nuno Sá
2026-06-23 10:27                     ` Andy Shevchenko
2026-06-23 14:14                       ` Frank Li
2026-06-24 15:33                       ` Nuno Sá [this message]
2026-06-24 16:49                         ` Frank Li
2026-06-16 15:40 ` [PATCH RFC 3/3] iio: buffer-dmaengine: Use dma_slave_caps width accessors Nuno Sá
2026-06-16 15:40   ` Nuno Sá via B4 Relay
2026-06-16 16:25   ` Frank Li
2026-06-17  9:57 ` [PATCH RFC 0/3] dmaengine: Support address bus widths of 32 bytes and above Andy Shevchenko
2026-06-17 14:19   ` Nuno Sá

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