From: Chao Liu <chao.liu.zevorn@gmail.com>
To: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, andrew.jones@oss.qualcomm.com,
leif.lindholm@oss.qualcomm.com, uwu@icenowy.me,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v8 6/7] tests/functional/riscv64: add riscv-server-ref TPM selftest
Date: Thu, 2 Jul 2026 22:48:22 +0800 [thread overview]
Message-ID: <akZ6LnH2X4NZ-cz8@ChaodeMacBook-Pro.local> (raw)
In-Reply-To: <20260610214133.1882563-7-daniel.barboza@oss.qualcomm.com>
On Wed, Jun 10, 2026 at 06:41:32PM +0800, Daniel Henrique Barboza wrote:
> Add a TPM specific selftest for the riscv-server-ref board. The test
> will be skipped if there's no 'swtpm' in the host.
>
> The test has been basically cloned from our Aspeed ast2600 friends.
> Shoutout to monsieur Cédric Le Goater for the code.
>
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> ---
> tests/functional/riscv64/test_server_ref.py | 31 ++++++++++++++++++++-
> 1 file changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/tests/functional/riscv64/test_server_ref.py b/tests/functional/riscv64/test_server_ref.py
> index 2ecfcf60ad..9b120628dc 100755
> --- a/tests/functional/riscv64/test_server_ref.py
> +++ b/tests/functional/riscv64/test_server_ref.py
> @@ -8,8 +8,13 @@
> riscv-server-ref board test
> """
>
> +import os
> +import tempfile
> +import subprocess
> +
> from qemu_test import QemuSystemTest, Asset
> from qemu_test import wait_for_console_pattern
> +from qemu_test import skipIfMissingCommands
>
> class RiscvServerRefTest(QemuSystemTest):
> """
> @@ -26,7 +31,7 @@ class RiscvServerRefTest(QemuSystemTest):
> 'master/riscv/images/virt64/buildroot/rootfs.ext2'),
> 'f00bb88749f945d80675540a1338bd1ccb226574685a5b6c65ab44027d0411a8')
>
> - def test_boot_linux_test(self):
> + def _test_boot_linux_test(self, tpmstate_dir=None):
> self.set_machine('riscv-server-ref')
> kernel_path = self.ASSET_KERNEL.fetch()
> rootfs_path = self.ASSET_ROOTFS.fetch()
> @@ -38,6 +43,22 @@ def test_boot_linux_test(self):
> self.vm.add_args('-device', 'ahci,id=ahci')
> self.vm.add_args('-device', 'ide-hd,drive=hd0,bus=ahci.0')
>
> + if tpmstate_dir is not None:
> + # Note: code taken verbatim from
> + # tests/functional/arm/test_aspeed_ast2600_buildroot_tpm.py
> +
> + # We must put the TPM state dir in /tmp/, not the build dir,
> + # because some distros use AppArmor to lock down swtpm and
> + # restrict the set of locations it can access files in.
> + socket = os.path.join(tpmstate_dir, 'swtpm-socket')
> + subprocess.run(['swtpm', 'socket', '-d', '--tpm2',
> + '--tpmstate', f'dir={tpmstate_dir}',
> + '--ctrl', f'type=unixio,path={socket}'],
> + check=True)
> + self.vm.add_args('-chardev', f'socket,id=chrtpm,path={socket}')
> + self.vm.add_args('-tpmdev', 'emulator,id=tpm0,chardev=chrtpm')
> + self.vm.add_args('-device', 'tpm-tis-device,tpmdev=tpm0')
> +
> self.vm.set_console()
> self.vm.launch()
>
> @@ -55,5 +76,13 @@ def test_boot_linux_test(self):
> # Wait for boot to complete - system reaches login prompt
> wait_for_console_pattern(self, 'Run /sbin/init as init process')
>
> + def test_boot_linux_test(self):
> + self._test_boot_linux_test()
> +
> + @skipIfMissingCommands('swtpm')
> + def test_boot_linux_test_tpm(self):
> + with tempfile.TemporaryDirectory(prefix="qemu_") as tpmstate_dir:
> + self._test_boot_linux_test(tpmstate_dir)
> +
> if __name__ == '__main__':
> QemuSystemTest.main()
> --
> 2.43.0
>
next prev parent reply other threads:[~2026-07-02 14:48 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-10 21:41 [PATCH v8 0/7] hw/riscv: Server Platform Reference Board Daniel Henrique Barboza
2026-06-10 21:41 ` [PATCH v8 1/7] target/riscv/cpu.c: remove 'bare' condition for .profile Daniel Henrique Barboza
2026-07-01 4:29 ` Joel Stanley
2026-07-02 13:41 ` Chao Liu
2026-06-10 21:41 ` [PATCH v8 2/7] target/riscv: add riscv-server-ref CPU Daniel Henrique Barboza
2026-06-16 0:57 ` Alistair Francis
2026-06-16 17:51 ` Matheus Ferst via
2026-06-16 17:51 ` Matheus Ferst via qemu development
2026-06-16 18:04 ` Daniel Henrique Barboza
2026-07-02 14:40 ` Chao Liu
2026-06-10 21:41 ` [PATCH v8 3/7] hw/riscv: server platform reference machine Daniel Henrique Barboza
2026-06-11 5:04 ` Sunil V L
2026-06-11 12:44 ` Daniel Henrique Barboza
2026-06-11 8:04 ` Nutty.Liu
2026-07-01 5:18 ` Joel Stanley
2026-06-10 21:41 ` [PATCH v8 4/7] tests/functional/riscv64: add riscv-server-ref tests Daniel Henrique Barboza
2026-06-11 6:39 ` Chao Liu
2026-06-11 8:09 ` Nutty.Liu
2026-06-16 0:59 ` Alistair Francis
2026-07-02 14:41 ` Chao Liu
2026-06-10 21:41 ` [PATCH v8 5/7] hw/riscv/server_platform_ref.c: add platform bus and TPM support Daniel Henrique Barboza
2026-06-16 1:06 ` Alistair Francis
2026-07-02 14:43 ` Chao Liu
2026-06-10 21:41 ` [PATCH v8 6/7] tests/functional/riscv64: add riscv-server-ref TPM selftest Daniel Henrique Barboza
2026-06-16 1:07 ` Alistair Francis
2026-07-01 5:31 ` Joel Stanley
2026-07-03 20:51 ` Daniel Henrique Barboza
2026-07-02 14:48 ` Chao Liu [this message]
2026-07-06 6:53 ` Philippe Mathieu-Daudé
2026-06-10 21:41 ` [PATCH v8 7/7] docs: add riscv-server-ref.rst Daniel Henrique Barboza
2026-06-16 1:09 ` Alistair Francis
2026-07-02 14:48 ` Chao Liu
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