From: Catalin Marinas <catalin.marinas@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Peter Maydell <peter.maydell@linaro.org>,
Joey Gouly <joey.gouly@arm.com>,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/3] arm64: Document missing bitfields in cpu-feature-registers.rst
Date: Thu, 2 Jul 2026 16:19:40 +0100 [thread overview]
Message-ID: <akaBjGtESDv_x6Ds@arm.com> (raw)
In-Reply-To: <20260522-arm64-cpu-ftr-regs-v1-2-19775b40faf0@kernel.org>
On Fri, May 22, 2026 at 06:58:38PM +0100, Mark Brown wrote:
> --- a/Documentation/arch/arm64/cpu-feature-registers.rst
> +++ b/Documentation/arch/arm64/cpu-feature-registers.rst
> @@ -113,6 +113,30 @@ infrastructure:
> 4. List of registers with visible features
> -------------------------------------------
>
> + ID_AA6FPFR0_EL1 - Floating Point feature ID register 0
That's missing a '4' in '64'.
> + ID_AA6SMFR0_EL1 - SME feature ID register 0
Same here.
--
Catalin
next prev parent reply other threads:[~2026-07-02 15:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-22 17:58 [PATCH 0/3] arm64: Fixes and cleanups for cpu-feature-registers.rst Mark Brown
2026-05-22 17:58 ` [PATCH 1/3] arm64: Don't number registers in cpu-feature-registers.rst Mark Brown
2026-05-22 17:58 ` [PATCH 2/3] arm64: Document missing bitfields " Mark Brown
2026-07-02 15:19 ` Catalin Marinas [this message]
2026-05-22 17:58 ` [PATCH 3/3] arm64: Sort registers " Mark Brown
2026-07-02 15:22 ` Catalin Marinas
2026-07-02 15:38 ` Mark Brown
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