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Sun, 05 Jul 2026 22:00:27 -0700 (PDT) Received: from localhost ([64.186.250.142]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30f1cbfc285sm38937415eec.5.2026.07.05.22.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jul 2026 22:00:27 -0700 (PDT) Date: Mon, 6 Jul 2026 13:00:24 +0800 From: Chao Liu To: Nicholas Piggin Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , bin.meng@windriver.com, vivahavey@gmail.com, Alvin Chang , Yu-Ming Chang , Joel Stanley Subject: Re: [RFC PATCH 04/25] target/riscv/debug: Fix icount trigger privilege check Message-ID: References: <20260114044701.1173347-1-npiggin@gmail.com> <20260114044701.1173347-5-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260114044701.1173347-5-npiggin@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pg1-x544.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Wed, Jan 14, 2026 at 02:46:37PM +0800, Nicholas Piggin wrote: > The check_itrigger_priv() did not check privilege bits properly. Move > all priv checks into functions and have the icount check follow the same > form as the others. > > Signed-off-by: Nicholas Piggin > --- > target/riscv/debug.c | 82 ++++++++++++++++++++------------------------ > 1 file changed, 37 insertions(+), 45 deletions(-) > > diff --git a/target/riscv/debug.c b/target/riscv/debug.c > index c92bd9860e..2effbb49af 100644 > --- a/target/riscv/debug.c > +++ b/target/riscv/debug.c > @@ -306,48 +306,50 @@ static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index) > * Check the privilege level of specific trigger matches CPU's current privilege > * level. > */ > +static bool type2_priv_match(CPURISCVState *env, target_ulong tdata1) > +{ > + /* type 2 trigger cannot be fired in VU/VS mode */ > + if (env->virt_enabled) { > + return false; > + } > + /* check U/S/M bit against current privilege level */ > + return (((tdata1 >> 3) & 0b1011) & BIT(env->priv)); > +} > + > +static bool type6_priv_match(CPURISCVState *env, target_ulong tdata1) > +{ > + if (env->virt_enabled) { > + /* check VU/VS bit against current privilege level */ > + return (((tdata1 >> 23) & 0b11) & BIT(env->priv)); > + } else { > + /* check U/S/M bit against current privilege level */ > + return (((tdata1 >> 3) & 0b1011) & BIT(env->priv)); > + } > +} The new logic looks correct to me, but now it uses open-coded shifts and masks to check the privilege bits. Since we already have these bits defined in debug.h, like `TYPE2_U/S/M`, `TYPE6_VU/VS/U/S/M` and `ITRIGGER_VU/VS/U/S/M`, I think it would be better to use those masks through a small helper instead of spelling out `>> 3`, `>> 6`, `>> 23` and `0b1011` here. That would make the code easier to read and maintain later. like: ``` static bool trigger_priv_bit_match(target_ulong tdata1, target_ulong u_mask, target_ulong s_mask, target_ulong m_mask, target_ulong priv) { switch (priv) { case PRV_U: return (tdata1 & u_mask) != 0; case PRV_S: return (tdata1 & s_mask) != 0; case PRV_M: return (tdata1 & m_mask) != 0; default: g_assert_not_reached(); } } static bool trigger_vpriv_bit_match(target_ulong tdata1, target_ulong vu_mask, target_ulong vs_mask, target_ulong priv) { switch (priv) { case PRV_U: return (tdata1 & vu_mask) != 0; case PRV_S: return (tdata1 & vs_mask) != 0; default: return false; } } ``` So we can call it this way: ``` static bool type2_priv_match(CPURISCVState *env, target_ulong tdata1) { /* type 2 trigger cannot be fired in VU/VS mode */ if (env->virt_enabled) { return false; } return trigger_priv_bit_match(tdata1, TYPE2_U, TYPE2_S, TYPE2_M, env->priv); } static bool type6_priv_match(CPURISCVState *env, target_ulong tdata1) { if (env->virt_enabled) { return trigger_vpriv_bit_match(tdata1, TYPE6_VU, TYPE6_VS, env->priv); } return trigger_priv_bit_match(tdata1, TYPE6_U, TYPE6_S, TYPE6_M, env->priv); } static bool icount_priv_match(CPURISCVState *env, target_ulong tdata1) { if (env->virt_enabled) { return trigger_vpriv_bit_match(tdata1, ITRIGGER_VU, ITRIGGER_VS, env->priv); } return trigger_priv_bit_match(tdata1, ITRIGGER_U, ITRIGGER_S, ITRIGGER_M, env->priv); } ``` And I don't mean going back to `get_field(mask) == env->priv`; that pattern is easy to get wrong for `PRV_U == 0`. The helper should just test the mask selected by the current privilege. Thanks, Chao > + > +static bool icount_priv_match(CPURISCVState *env, target_ulong tdata1) > +{ > + if (env->virt_enabled) { > + /* check VU/VS bit against current privilege level */ > + return (((tdata1 >> 25) & 0b11) & BIT(env->priv)); > + } else { > + /* check U/S/M bit against current privilege level */ > + return (((tdata1 >> 6) & 0b1011) & BIT(env->priv)); > + } > +} > + > static bool trigger_priv_match(CPURISCVState *env, trigger_type_t type, > int trigger_index) > { > - target_ulong ctrl = env->tdata1[trigger_index]; > + target_ulong tdata1 = env->tdata1[trigger_index]; > > switch (type) { > case TRIGGER_TYPE_AD_MATCH: > - /* type 2 trigger cannot be fired in VU/VS mode */ > - if (env->virt_enabled) { > - return false; > - } > - /* check U/S/M bit against current privilege level */ > - if ((ctrl >> 3) & BIT(env->priv)) { > - return true; > - } > - break; > + return type2_priv_match(env, tdata1); > case TRIGGER_TYPE_AD_MATCH6: > - if (env->virt_enabled) { > - /* check VU/VS bit against current privilege level */ > - if ((ctrl >> 23) & BIT(env->priv)) { > - return true; > - } > - } else { > - /* check U/S/M bit against current privilege level */ > - if ((ctrl >> 3) & BIT(env->priv)) { > - return true; > - } > - } > - break; > + return type6_priv_match(env, tdata1); > case TRIGGER_TYPE_INST_CNT: > - if (env->virt_enabled) { > - /* check VU/VS bit against current privilege level */ > - if ((ctrl >> 25) & BIT(env->priv)) { > - return true; > - } > - } else { > - /* check U/S/M bit against current privilege level */ > - if ((ctrl >> 6) & BIT(env->priv)) { > - return true; > - } > - } > - break; > + return icount_priv_match(env, tdata1); > case TRIGGER_TYPE_INT: > case TRIGGER_TYPE_EXCP: > case TRIGGER_TYPE_EXT_SRC: > @@ -665,17 +667,7 @@ itrigger_set_count(CPURISCVState *env, int index, int value) > > static bool check_itrigger_priv(CPURISCVState *env, int index) > { > - target_ulong tdata1 = env->tdata1[index]; > - if (env->virt_enabled) { > - /* check VU/VS bit against current privilege level */ > - return (get_field(tdata1, ITRIGGER_VS) == env->priv) || > - (get_field(tdata1, ITRIGGER_VU) == env->priv); > - } else { > - /* check U/S/M bit against current privilege level */ > - return (get_field(tdata1, ITRIGGER_M) == env->priv) || > - (get_field(tdata1, ITRIGGER_S) == env->priv) || > - (get_field(tdata1, ITRIGGER_U) == env->priv); > - } > + return icount_priv_match(env, index); > } > > bool riscv_itrigger_enabled(CPURISCVState *env) > -- > 2.51.0 > >