Re: [PATCH v6 0/9] target/riscv: Add RISC-V Zvfofp8min extension support

[Max Chou <max.chou@sifive.com>]

Gental ping.

On 2026-07-09 00:18, Max Chou wrote:
> This patchset adds support for the RISC-V Zvfofp8min ISA extension that
> provides conversion operations for OCP FP8 formats which provide the
> foundation for the future vector matrix extensions.
> 
> Ratification status:
> - Zvfofp8min is currently v0.9 and is going through the RVIA ratification
>   process. This series tracks the v0.9 isa-manual tag below.
> - riscv-isa-manual tag:
>   https://github.com/riscv/riscv-isa-manual/releases/tag/zvfofp8min-0.9
> 
> Zvfofp8min (v0.9):
> - The Zvfofp8min extension provides minimal vector conversion support for
>   the OFP8 formats. It requires the Zve32f extension and leverages the
>   altfmt field in the VTYPE CSR (introduced by Zvfbfa) to select between
>   E4M3 (altfmt=0) and E5M2 (altfmt=1) formats. Per the OCP FP8 spec and
>   the extension definition:
>   - Canonical NaN for both E4M3 and E5M2 is 0x7f.
>   - All NaNs are treated as quiet NaNs.
>   - Widening conversions are exact: no rounding and no exception flags.
> - These conversions are the data-movement primitives that feed and drain
>   the OFP8 vector/matrix compute pipeline.
> - The LLVM RISC-V backend emits these instructions as of LLVM 22.1.0:
>   https://releases.llvm.org/22.1.0/docs/ReleaseNotes.html#changes-to-the-risc-v-backend
> 
> Instructions:
>   Extended (existing instructions taught to handle OFP8):
>   - vfwcvtbf16.f.f.v   : OFP8 to BF16 widening conversion
>   - vfncvtbf16.f.f.w   : BF16 to OFP8 narrowing conversion
>   New:
>   - vfncvtbf16.sat.f.f.w : BF16 to OFP8 narrowing with saturation
>   - vfncvt.f.f.q         : FP32 to OFP8 quad-width (4x) narrowing conversion
>   - vfncvt.sat.f.f.q     : FP32 to OFP8 quad-width narrowing with saturation
> 
> Verification:
> - riscv-tests (fork https://github.com/riscv-software-src/riscv-tests):
>   https://github.com/rnax/riscv-tests/tree/dev/rnax/support_zvfofp8min
>   - Require LLVM 22.1.0
>     https://releases.llvm.org/22.1.0/docs/ReleaseNotes.html#changes-to-the-risc-v-backend
>   - Zvfofp8min test target: rv64uzvfofp8min/rv32uzvfofp8min
>   - Both Spike and QEMU applied this patchset could pass the riscv-tests
> 
> References:
> - OCP FP8 specification:
>   https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-12-01-pdf-1
> 
> 
> Changes in v6
> - Add patch 1 to fix the biased exponent write bug in the
>   parts_float_to_e5m2() saturate path. FloatParts64.exp holds an
>   unbiased exponent, so exp_bias must be subtracted when storing
>   the max-normal biased exponent value.
> - Initialize float_e4m3_nan_is_snan to false in riscv_cpu_reset_hold()
>   to ensure consistent NaN handling for OFP8 E4M3 operations.
> - Merge "Expose Zvfofp8min property" into "Add cfg property for
>   Zvfofp8min extension" to keep the property registration together
>   with the cfg field definition.
> - Fix indentation of cbo.* opcode table entries in the disas patch.
> - Rebase on riscv-to-apply.next (commit 267b5a2)
> 
> Changes in v5
> - Drop Zvfofp4min which is not going through the RVIA ratification
>   process yet.
> - Fix typos.
> - Rebase on riscv-to-apply.next (commit bf76a00)
> 
> Changes in v4
> - Rebase on riscv-to-apply.next (commit 21101a7)
> - Remove the softfloat library related patches (Thanks for RH's help to
>   split this part)
> - Add missing illegal ALTFMT SEW pattern checking for Zvfofp8min in
>   patch 4 (target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16
>   conversion for Zvfofp8min extension)
> 
> Changes in v3
> - Add floatN_nan_is_snan to simply the quiet/signaling NaN checking flow
>   in patch 2 & 3
> - Add patch 4 to fix pseudo-NaN handling in FPATAN/FYL2XP1/FYL2X helpers
> 
> Changes in v2
> - Merged v1 patch 2 & 3 to v2 patch 3, v1 patch 4 & 5 to v2 patch 4
> - Added new v2 patch 2 to refactor the IEEE format NaN classification
>   functions (float16, bfloat16, float32, float64) to use internal helper
>   functions, reducing code duplication and improving maintainability.
>   The OCP FP8 NaN classification functions follow the same pattern.
> - Refactored softfloat implementation to use capability-based FloatFmt
>   flags (no_infinity, limited_nan, overflow_raises_invalid, normal_frac_max)
>   instead of monolithic flags
> - Removed ocp_fp8e5m2_no_signal_nan and ocp_fp8_same_canonical_nan flags
>   from float_status; now using local float_status with no_signaling_nans
>   and default_nan_pattern for RISC-V Zvfofp8min instructions
> - Rebased on latest riscv-to-apply.next with zvfbfa v3 patchset
> 
> v5: 20260427060928.2322570-1-max.chou@sifive.com
> v4: 20260304134006.2908449-1-max.chou@sifive.com
> v3: 20260204051756.667397-1-max.chou@sifive.com
> v2: 20260127063723.442734-1-max.chou@sifive.com
> v1: 20260108151650.16329-1-max.chou@sifive.com
> 
> 
> Max Chou (9):
>   fpu: Fix biased exponent write in parts_float_to_e5m2 saturate path
>   target/riscv: rvv: Fix NOP_UU_B vs2 width
>   target/riscv: Add cfg property for Zvfofp8min extension
>   target/riscv: Add implied rules for Zvfofp8min extension
>   target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16
>     conversion for Zvfofp8min extension
>   target/riscv: rvv: Make vfncvtbf16.f.f.w support BF16 to OFP8
>     conversion for Zvfofp8min extension
>   target/riscv: rvv: Add vfncvtbf16.sat.f.f.w instruction for Zvfofp8min
>     extension
>   target/riscv: rvv: Add vfncvt.f.f.q and vfncvt.sat.f.f.q instructions
>     for Zvfofp8min extension
>   disas/riscv: Add support of Zvfofp8min extension
> 
>  disas/riscv.c                                 |  19 ++-
>  fpu/softfloat.c                               |   3 +-
>  target/riscv/cpu.c                            |  13 +-
>  target/riscv/cpu_cfg_fields.h.inc             |   1 +
>  target/riscv/helper.h                         |  12 ++
>  target/riscv/insn32.decode                    |   5 +
>  .../riscv/tcg/insn_trans/trans_rvbf16.c.inc   |  32 +++--
>  .../riscv/tcg/insn_trans/trans_rvofp8.c.inc   | 105 +++++++++++++++
>  target/riscv/tcg/insn_trans/trans_rvv.c.inc   |  40 ++++++
>  target/riscv/tcg/tcg-cpu.c                    |   5 +
>  target/riscv/tcg/translate.c                  |   1 +
>  target/riscv/tcg/vector_helper.c              | 120 +++++++++++++++++-
>  12 files changed, 338 insertions(+), 18 deletions(-)
>  create mode 100644 target/riscv/tcg/insn_trans/trans_rvofp8.c.inc
> 
> -- 
> 2.55.0
>