Re: [PATCH v2 3/3] KVM: x86: Flush guest TLB on MTRR MSR writes

[Sean Christopherson <seanjc@google.com>]

On Fri, Jul 17, 2026, Jim Mattson wrote:
> Per both the AMD APM and the Intel SDM, writing to an MTRR with WRMSR is an
> implicit TLB invalidation that invalidates all TLB entries (including
> global entries). [The APM uses the word, "update," which could be construed
> to mean "modify," but it is unclear.]

Yeesh, the SDM isn't very helpful.  Under the description of WRMSR, it very clearly
says:

  When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated.

But then in the recommended pseudocode, the SDM says software should flush TLBs:

  pre_mtrr_change()
    BEGIN
      disable interrupts;
      Save current value of CR4;
      disable and flush caches;
      flush TLBs;
      disable MTRRs;
      IF multiprocessing
        THEN maintain consistency through IPIs;
      FI;
    END
  
  post_mtrr_change()
    BEGIN
      flush caches and TLBs;
      enable MTRRs;
      enable caches;
      restore value of CR4;
      enable interrupts;
    END

> Previously, kvm_mtrr_set_msr() stored the updated MTRR state without
> requesting a TLB flush. This broke x86 architectural compliance by leaving
> existing TLB entries in hardware. Additionally, on AMD CPUs supporting
> ERAPS, omitting the TLB flush request meant VCPU_REG_ERAPS was never
> dirtied on MTRR writes, leaving the Return Address Predictor (RAP/RSB)
> uncleared.

Heh, Andy Cooper even pointed out the implicit flushes on MTRR writes[1], and no
one noticed KVM was missing that specific flush.  I mention that mostly because
the context of that thread was asking AMD to drop the statement that the RAP is
cleared on writes to "other model specific MSRs, see NDA docs", so that hypervisors
wouldn't have to clear the RAP on every WRMSR.

AMD updated their documentation[2] to say that clears on MSR writes are considered
microarchitectural, but this patch and the above blurb are still accurate because
MTRR writes are covered by the "implicit TLB flush" clause, not the generic WRMSR
clause.

[1] https://lore.kernel.org/all/1c76cb00-1fe1-4fd0-b7b9-86ddca6115ba@citrix.com
[2] https://lore.kernel.org/all/08826b5879e2d9c354424279763d3ce5556f44cc.camel@amd.com

> Issue a KVM_REQ_TLB_FLUSH_GUEST request on every MTRR MSR write to match
> x86 architectural semantics.
> 
> Fixes: 9ba075a664df ("KVM: MTRR support")
> Assisted-by: Gemini:Gemini-Next
> Signed-off-by: Jim Mattson <jmattson@google.com>
> ---
>  arch/x86/kvm/mtrr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/kvm/mtrr.c b/arch/x86/kvm/mtrr.c
> index 6f74e2b27c1e..ca5e5c7f7022 100644
> --- a/arch/x86/kvm/mtrr.c
> +++ b/arch/x86/kvm/mtrr.c
> @@ -105,6 +105,7 @@ int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
>  		return 1;
>  
>  	*mtrr = data;
> +	kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
>  	return 0;
>  }
>  
> -- 
> 2.55.0.229.g6434b31f56-goog
>