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Thu, 9 Jul 2026 14:32:21 -0700 Date: Thu, 9 Jul 2026 14:32:19 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , "Joerg Roedel (AMD)" , Jean-Philippe Brucker , , Robin Murphy , Will Deacon , David Matlack , "Pasha Tatashin" , , "Pranjal Shrivastava" , Samiullah Khawaja , Mostafa Saleh Subject: Re: [PATCH v2 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Message-ID: References: <0-v2-43074a57a53a+fb95-smmu_tlbi_jgg@nvidia.com> <7-v2-43074a57a53a+fb95-smmu_tlbi_jgg@nvidia.com> <20260709182559.GH422027@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260709182559.GH422027@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC0:EE_|SN7PR12MB6931:EE_ X-MS-Office365-Filtering-Correlation-Id: 2ad62401-16f3-4e55-454b-08dede019c21 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700016|23010399003|11063799006|4143699003|22082099003|56012099006|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YRJO9Wc+1/T7F3yFGWiUGWufyFJ4BLzfL0AsQWhve/y+9AVa3TG1n6qTdPCDgsR4CVMxMOFmv39F+TBQ3TQYntdeIjnerJt5q0i60bgDrcJTeJGgkD2cSCT/M2NbbwZt9r17ES3If7H3ysEQiSbs9COMVUBoM70MaRIt13C85ejH3tNjpj993ht24CRcDm/uGk8Qe5HuihBUgFjmQ4g0/mb2sfsLTYlee6fTPjFpIOCIs1pAMD9yD24nfjX9dv/OcS/5/upYcSQHiuLBG7s1MJuzCFkgNJz4fAqggRFWc3B37dQemlfI1Q4hhurlTLxrVL62c41UKlBXLYdwQwUaePPckQaZqbhoN2XKeYh6+Lltgv1dIZfoYDcPCDEUnl5IaykY3duwb3L1ETHDf9O+IG9A2uesYmingTSfc8+TiIORrlpJtxL+ZFhq1SgxxRY0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2026 21:32:42.7592 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ad62401-16f3-4e55-454b-08dede019c21 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6931 On Thu, Jul 09, 2026 at 03:25:59PM -0300, Jason Gunthorpe wrote: > I wonder if this Claude was thinking about a kernel before > 84b2baf427968c1 where this flow would have been as-described? You are right! I applied the patches on 7.2-rc1, but somehow AI was still relying on the old code. I had a some hard time to fully get it.. > With the kernel today the arm_smmu_tlb_inv_walk() is supposed to clear > out the walk cache before freeing the table entry and the gather is > supposed to clear out the leaf entries themselves. 84b2baf427968c1 > changed things so we always have a second leaf-only gather that covers > the entire unmap range, which also introduced the double invalidation. IIUIC, for the "double invalidation", the driver currently flushes: 1. tlb_flush_walk(iova, size=2M, granule=4K, leaf-only=false) // flush both walk cache and leaf entries 2.iommu_iotlb_sync((iova, size=2M, granule=2M, leaf-only=true) // flush the 1st leaf entry only > What I missed is that because of that commit gather->pgsize is no > longer correct, it will be 2M even if __arm_lpae_free_pgtable() > unmapped 4k leaves. So we will still miss leaf invalidation :\ This also makes sense to me. > > > + * If leaf_levels_bitmap is 0 then this is a walk cache only > > > + * invalidation. > > [...] > > > + u8 leaf_levels_bitmap; > > > > Or is that only to implement a walkcache-only invalidation, such > > that the leaf entries will have separate invalidation call(s)? > > That was the plan I see the full picture now. Thanks Nicolin