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[82.132.237.191]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47aa039bcdasm62425706f8f.21.2026.07.10.05.52.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 05:52:05 -0700 (PDT) Date: Fri, 10 Jul 2026 13:52:02 +0100 From: Jim MacArthur To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Richard Henderson Subject: Re: [PATCH v3 4/6] target/arm/cpu-features.h: x-rme now means GPC3 Message-ID: References: <20260618-jmac-gpc3b-v3-0-353e546067e7@linaro.org> <20260618-jmac-gpc3b-v3-4-353e546067e7@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=jim.macarthur@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Mon, Jun 29, 2026 at 01:00:05PM +0100, Peter Maydell wrote: > On Thu, 18 Jun 2026 at 17:33, Jim MacArthur wrote: > > > > Reviewed-by: Richard Henderson > > Signed-off-by: Jim MacArthur > > --- > > target/arm/tcg/cpu64.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > > index f7a920a202..75c2027900 100644 > > --- a/target/arm/tcg/cpu64.c > > +++ b/target/arm/tcg/cpu64.c > > @@ -159,8 +159,8 @@ static void cpu_arm_set_rme(Object *obj, bool value, Error **errp) > > { > > ARMCPU *cpu = ARM_CPU(obj); > > > > - /* Enable FEAT_RME_GPC2 */ > > - FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, RME, value ? 2 : 0); > > + /* Enable FEAT_RME_GPC3 */ > > + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, RME, value ? 3 : 0); > > } > > Just noticed this, but does this mean we should now list > FEAT_RME_GPC3 in docs/system/arm/emulation.rst ? > (If so, we can fix that as a followup patch.) > Looking at this again, we don't currently implement the APAS instruction which is a necessary part of FEAT_RME_GPC3, so probably shouldn't advertise that in the documentation yet. I'm unsure how to handle this instruction at the moment; it might be that we can simply decode it and ignore it, in which case I can easily make up another patch to complete FEAT_RME_GPC3, but if not I'll need to seek further advice. Jim