From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D225946AF03 for ; Tue, 14 Jul 2026 13:43:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784036598; cv=none; b=RwbF6yEO7yPGA9rQhvNp+PYCjfw1crSwiWY2GLx5st03CbrXpzqvIHxP8C1GF70CepahS9slciQZQsMNBLVrtFBVc1gJuui19UEYIKaevT8ktEb5kDT0xUFf4R1jT+dM66S6TDof3BW0wnhTiwioLAA0gz9JWbKjA5ZnMYjhaqo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784036598; c=relaxed/simple; bh=XEGCQNz6DX9A+EjN/qbl6Yj1SrGTd3gPqQ0Y8PcOT4U=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=D5zEieVlepKjkcuYh2DDnpYpW2mWaH2rxdHQseZsNsgPnCwBqbpW3wd+K1KX6d/itegnXxZl6BTh0sW4BHACl5b80L3Is5m0pPSYOr6e92G14gKu1bO9jx2Aqyfl8i2HHieCYVypC0oNEGOvQK6xI9Qypvy+YI3JsYLCaIggU7s= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=WhqFm/n/; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="WhqFm/n/" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9E0412F; Tue, 14 Jul 2026 06:43:04 -0700 (PDT) Received: from localhost (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2CFCC3F93E; Tue, 14 Jul 2026 06:43:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784036588; bh=XEGCQNz6DX9A+EjN/qbl6Yj1SrGTd3gPqQ0Y8PcOT4U=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=WhqFm/n/5K02i+v6vOAuVrgmcsgHSQy3l9WkMK/HNMdTZFgjuafGCWt5eNi3m16hU 200Q3vUxqRdElXyOsQiwxtLFXbgofGRO/fgjs8kEK02OkqeI3V6xrAZddcP9Jp3UO5 nfER6AyYELi/rjZ/i0+m3PoIxHyYn3eDSMsj9lZ0= Date: Tue, 14 Jul 2026 19:13:05 +0530 From: Linu Cherian To: Suzuki K Poulose Cc: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list Message-ID: References: <20260708144331.679816-1-linu.cherian@arm.com> <20260708144331.679816-4-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Jul 08, 2026 at 03:53:59PM +0100, Suzuki K Poulose wrote: > On 08/07/2026 15:43, Linu Cherian wrote: > > Add below cpus to the midr list, which supports > > BBML2_NOABORT. > > > > Cortex A520(AE) > > Cortex A715 > > Cortex A720(AE) > > Cortex A725 > > Neoverse N3 > > C1-Nano > > C1-Pro > > C1-Ultra > > C1-Premium > > > > C1-Ultra and C1-Premium both suffer from erratum 3683289, > > where Break-Before-Make must be followed to avoid a livelock. > > For both CPUs, the erratum is fixed from r1p1. > > Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0. > > Please could you also update the list of errata here : > > Documentation/arch/arm64/silicon-errata.rst Ack. > > > > > The relevant SDENs are: > > * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/ > > * C1-Premium: https://developer.arm.com/documentation/111078/9-00/ > > > > Signed-off-by: Linu Cherian > > --- > > arch/arm64/kernel/cpufeature.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index 9a22df0c5120..adcabea80fcb 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -2152,6 +2152,15 @@ bool cpu_supports_bbml2_noabort(void) > > MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), > > MIDR_ALL_VERSIONS(MIDR_AMPERE1), > > MIDR_ALL_VERSIONS(MIDR_AMPERE1A), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), > > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), > > + MIDR_ALL_VERSIONS(MIDR_C1_NANO), > > + MIDR_ALL_VERSIONS(MIDR_C1_PRO), > > And mention it here, so that it is evident from the code alone ? > Ack. > > + MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf), > > + MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf), > > > Suzuki > > > > {} > > }; >