From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 706D6370D6E for ; Tue, 14 Jul 2026 14:01:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784037668; cv=none; b=WHHNARV2aNK3Vk+b2Y3aG1BL7IhsZPbcSbj5K/5JRYordrELNzV5hKYyj7cF5hT82ObR2PLG7JG/XGBPi0lW34cYoG0jnhDxNspE4TtcCaFDdUHyX2fZ3wb+McMi2vZabL7N93xLm88oznSy0BiEIIjLWSn9RrT56/0t4U7B0s8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784037668; c=relaxed/simple; bh=9Sq26LWHI8r58EN8DYRUbljc1HREA/LJnj9Grw6C71A=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=L6fAb8TcXyMrp2DFB7ho4IcTDuTScsbp9pWhZ0Tig+NqrUmT/MoQFZtSIWMdjFqFjXcyMsrx/TQiMtFrBf5Ph+29ll9+fGfzwIJSALpCCxUgu68R6cJnPDkBqxUcaCek8nFceb1EkD9hVO7/0HO9YcoVR6S4VvINxi3T47VhlKs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=REpG6w4R; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="REpG6w4R" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 12CA62F; Tue, 14 Jul 2026 07:01:01 -0700 (PDT) Received: from localhost (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 987C83F915; Tue, 14 Jul 2026 07:01:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784037665; bh=9Sq26LWHI8r58EN8DYRUbljc1HREA/LJnj9Grw6C71A=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=REpG6w4RRhMpa2frJH6lKCpfMm5hBL1jNODY14Ih3xa6nFlixOZOgxITV028keuHd ihvdKTp171/10HMHfFAPIOqzguzYYMuv04354I1RUVpDd3SazCk9jBj3IwWv1n+tUl zPWlsbiC+gjqqvdff4sH/HJWcz0nToFWnlikqDVU= Date: Tue, 14 Jul 2026 19:31:01 +0530 From: Linu Cherian To: Anshuman Khandual Cc: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Suzuki K Poulose , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 6/6] arm64: cpufeature: Detect BBML3 based on MMFR2 ID Message-ID: References: <20260708144331.679816-1-linu.cherian@arm.com> <20260708144331.679816-7-linu.cherian@arm.com> <11d99a7c-50f9-4a4d-a75b-ef11cf3371af@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <11d99a7c-50f9-4a4d-a75b-ef11cf3371af@arm.com> Hi, On Fri, Jul 10, 2026 at 12:41:57PM +0530, Anshuman Khandual wrote: > Please do mention full register field here > > arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM > > On 08/07/26 8:13 PM, Linu Cherian wrote: > > Add MMFR2 ID based BBML3 feature detection, so > > Ditto ^^^^^^^^^^^^ > > > that compliant cpus doesn't need to be added to the > > midr list. > > Could be reworded as : > > Add ID_AA64MMFR2_EL1.BBM based BBML3 feature detection in > cpu_supports_bbml3() so that cpus with the feature would > not have to be added into MIDR based supports_bbml3_list. > Okay, will change. > > > > Signed-off-by: Linu Cherian > > --- > > arch/arm64/kernel/cpufeature.c | 17 +++++++++-------- > > 1 file changed, 9 insertions(+), 8 deletions(-) > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index e9ecaa036479..3f4a36f152d0 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -2133,6 +2133,12 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, > > > > bool cpu_supports_bbml3(void) > > { > > + u64 mmfr2; > > + > > + mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); > > + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) > > + return true; > > + > > /* CPUs that support BBML3 but dont advertise through MMFR2 ID */ > > static const struct midr_range supports_bbml3_list[] = { > > MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), > > @@ -2153,15 +2159,10 @@ bool cpu_supports_bbml3(void) > > {} > > }; > > > > - if (!is_midr_in_range_list(supports_bbml3_list)) > > - return false; > > - > > - /* > > - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care > > - * about whether the MIDR check passes. > > - */ > > + if (is_midr_in_range_list(supports_bbml3_list)) > > + return true; > > > > - return true; > > + return false; > > } > > > > static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) > > With the minor changes to the commit message above. > > Reviewed-by: Anshuman Khandual