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Wed, 15 Jul 2026 06:36:55 -0700 (PDT) Received: from owl5 ([2001:861:3201:3d10:e682:163f:4878:db7e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f462e0cb2sm16802692f8f.0.2026.07.15.06.36.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 06:36:54 -0700 (PDT) Date: Wed, 15 Jul 2026 15:36:53 +0200 From: Gary Bisson To: AngeloGioacchino Del Regno Cc: Esben Haabendal , Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Adam Thiede , Thorsten Leemhuis Subject: Re: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable Message-ID: References: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com> <8733xko1ms.fsf@geanix.com> <0f719c00-3cf5-4403-afbf-713b07255981@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0f719c00-3cf5-4403-afbf-713b07255981@collabora.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, On Wed, Jul 15, 2026 at 03:25:11PM +0200, AngeloGioacchino Del Regno wrote: > On 7/15/26 14:53, Esben Haabendal wrote: > > Gary Bisson writes: > > > > > Some bridges, such as the TI SN65DSI83, require the HS clock to be > > > running in order to lock its PLL during its own pre-enable function. > > > > > > Without this change, the bridge gives the following error: > > > sn65dsi83 14-002c: failed to lock PLL, ret=-110 > > > sn65dsi83 14-002c: Unexpected link status 0x01 > > > sn65dsi83 14-002c: reset the pipe > > > > > > Move the necessary functions from enable to pre-enable. > > > > > > Signed-off-by: Gary Bisson > > > > Hi > > > > I have run into the same problem, but in combination with another > > pipeline. I am seeing same problem with an i.MX8 using the nwl-dsi > > bridge and the dcss driver. > > > > I have submitted a fix that adresses the problem in the ti-sn65dsi83 > > driver instead. With a bit of luck, it can replace the fix proposed in > > this thread. > > > > See https://lore.kernel.org/all/20260711-ti-sn65dsi83-fixes-v1-2-d85eb5342b98@geanix.com/ Thanks, just tried it on 7.2-rc3 with my patch reverted and confirm that it works too. My assumption was that the SN65DSI83 was locking the PLL earlier for some specific reason and therefore was reluctant to change it. > > /Esben > > That clarifies a lot of things. > > The patch on mtk_dsi shall be reverted then. Angelo, do you want me to offer the revert patch? Should I wait to see how the other thread goes? Regards, Gary