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Wed, 15 Jul 2026 06:52:24 -0700 (PDT) Received: from owl5 ([2001:861:3201:3d10:e682:163f:4878:db7e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4953c6fe0c6sm52050755e9.1.2026.07.15.06.52.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 06:52:24 -0700 (PDT) Date: Wed, 15 Jul 2026 15:52:22 +0200 From: Gary Bisson To: Luca Ceresoli Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Esben Haabendal , frieder.schrempf@kontron.de Subject: Re: [PATCH 2/2] drm/bridge: ti-sn65dsi83: Fix problem with premature PLL locking Message-ID: References: <20260711-ti-sn65dsi83-fixes-v1-0-d85eb5342b98@geanix.com> <20260711-ti-sn65dsi83-fixes-v1-2-d85eb5342b98@geanix.com> <178410553814.253594.6153852459811911516.b4-review@b4> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <178410553814.253594.6153852459811911516.b4-review@b4> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Esben and Luca, On Wed, Jul 15, 2026 at 10:52:18AM +0200, Luca Ceresoli wrote: > On Sat, 11 Jul 2026 13:51:15 +0200, Esben Haabendal wrote: > > Hi Esben, > > +Cc Gary > > > [...] > > > > This is the same issue as addressed in the patch by Gary Bisson [1], > > but changing the ti-sn65dsi83 driver instead, so we don't have to change > > all other drivers that could potentially be used with this chip. > > > > [1] https://lore.kernel.org/all/20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com/ > > AFAICU your patch would replace Gary's one. Also Gary's patch has been > reported to introduce regressions but it hasn't been reverted yet. Can you > reply to that thread mentioning your patch, so everybody in the discussion > is aware of your alternative proposal? Thanks for including me. I just tested this change and reverted my other one (mtk_dsi) and confirm that it works on my Tungsten510 + SN65DSI83 + tm070jdhg30 panel. Tested-by: Gary Bisson Note that the sn65dsi83 driver wasn't changed as I thought the PLL lock in pre-enable was on purpose. It was introduced by Frieder with this commit. Adding him to the thread to weigh in. dd9e329af723 drm/bridge: ti-sn65dsi83: Fix enable/disable flow to meet spec Regards, Gary