Re: [PATCH v2 2/3] arm64: dts: qcom: kodiak: move dp data-lanes to SoC dtsi

[Bjorn Andersson <andersson@kernel.org>]

On Sun, Jun 28, 2026 at 02:17:33PM +0300, Dmitry Baryshkov wrote:
> On Sun, 28 Jun 2026 at 05:26, Bjorn Andersson <andersson@kernel.org> wrote:
> >
> > On Fri, Jun 26, 2026 at 11:50:40PM +0300, Dmitry Baryshkov wrote:
> > > On Wed, Apr 29, 2026 at 12:10:41PM +0530, Mahadevan P wrote:
> > > > From: Mahadevan P <mahap@qti.qualcomm.com>
> > > >
> > > > The connection between the QMP Combo PHY and the DisplayPort controller
> > > > is fixed in SoC, so move the data-lanes property to kodiak.dtsi and
> > > > drop the per-board overrides.
> > > >
> > > > Also remove the redundant remote-endpoint cross-links and
> > > > orientation-switch property from qcs6490-rb3gen2 and
> > > > qcs6490-thundercomm-rubikpi3, which are already defined in kodiak.dtsi.
> > >
> > > Separate commit.
> > >
> > > >
> > > > Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
> > > > ---
> > > >  arch/arm64/boot/dts/qcom/kodiak.dtsi                          |  1 +
> > > >  arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts            |  4 ----
> > > >  arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts         |  4 ----
> > > >  arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts                  | 11 -----------
> > > >  arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts |  1 -
> > > >  arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts     |  3 ---
> > > >  arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi                |  1 -
> > > >  7 files changed, 1 insertion(+), 24 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> > > > index 96ac3656ab5a..0acc6917d7aa 100644
> > > > --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
> > > > +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> > > > @@ -5704,6 +5704,7 @@ dp_in: endpoint {
> > > >                                     port@1 {
> > > >                                             reg = <1>;
> > > >                                             mdss_dp_out: endpoint {
> > > > +                                                   data-lanes = <0 1>;
> > >
> > > This is not true. The SoC has 4 lanes going from the DP controller to
> > > the QMP PHY.
> > >
> >
> > Does this property really denote the number of lanes and mapping the
> > internal pipe between DP TX and PHY? Doesn't it tell how the external
> > mapping looks like?
> 
> The external mappings are described as a part of the QMP PHY (see
> sc7180-ecs-liva-qc710.dts as one of the recent examples). On the other
> hand, this property should describe the internal mappings (i.e.
> platforms should have 4 lanes here, in some cases in a weird order,
> like talos.dtsi).
> 

But this then denotes the internal mapping, within the SoC. In what
cases is that not a constant for the given SoC?

> Ideally SC7280 Herobrine should be updated to follow the current
> style, but it is complicated as almost nobody has the actual hardware.
> 

The "problem" Herobrine is that the DP vs USB pins are hard-wired on the
PCB, so you will always only have the fixed 2+2 configuration. The
"internal" mapping should be the same as on all other targets, but I
presume we claim that there's only 2 lanes internally to inform the OS
that it doesn't have the capability of driving 4 lanes of DP?

Regards,
Bjorn

> -- 
> With best wishes
> Dmitry