From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CC873C1963; Fri, 17 Jul 2026 09:36:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784280974; cv=none; b=aFUiR8TwfWYWrNOrGrqLFUQbHzt5/R6pcVaOFUUXRNiXOCDXm+JWoQ193MRZlhfVtr6zW9oxPlITJCJi8usmAEkdjJHTkiceMAA4ajKb2tQHm6h8lQ+nj+LPQnVOv29OvkeyS3OLJsz00I3gjgcENRW63FkGOA9/u2fcTNDpJ64= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784280974; c=relaxed/simple; bh=T7d7DbVj1KVILjFO4JDOyM8DC0u0gMs6qMPFYFp5N7g=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=UvQWfiD3G+Z8q//HnT3LEXzbRe06TFXSCK2Xos7E12CVgd0U/t0YRDy1AU6bWw2WCOwCQ9fZlrBxKpjoVpFwDFlQWRzkxBnJIf0zl/+oVQES4ddP2suoouVaxw2adH1fgV04x5UmE8Sf5ud6/+h1w1SU+nU2HROKZmajpyDfIdA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mivA6wmE; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mivA6wmE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F6161F000E9; Fri, 17 Jul 2026 09:36:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784280973; bh=vYE03cFrAt8vdmr6cI+rtww1tXHpE7MO8aZWnz4n5IE=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=mivA6wmEnf0kSCS+8EDtd4b9FFOk4PBKB78Ey4Mq+axl3p95/+7sI88cw7AH/E46C WbfjhzjxxCwC4Umx956jIqzXaPzLtEhU/LpeJi34xzlWE2ugDP/5ASVvJfewEbP0Oh VwlIq3NhpA01L10Yv8DNi+iZnLM5YidkNw0Eq3KBcHbjSrK3wb3RFh2X7p2TK5b6PZ w+Jb8SGA7K4u+lG0lvWqEZtQIDuTH8QzzRft5GvHEx4p2H56q8iy/je3WYizmvta3O R7qQ8AVTFO9yyn8Jg3lgiTRqCOFICZ9nT0Aj3w47dB8k+PoohPYWkLJB48tWxR/t5g CBrRUpTbV1x1A== Date: Fri, 17 Jul 2026 11:36:09 +0200 From: Ingo Molnar To: Borislav Petkov Cc: linux-kernel@vger.kernel.org, linux-tip-commits@vger.kernel.org, Juergen Gross , x86@kernel.org Subject: Re: [tip: x86/msr] x86/cpu: Stop using 32-bit MSR interfaces Message-ID: References: <20260629060526.3638272-20-jgross@suse.com> <178298735495.3843924.289690164073708304.tip-bot2@tip-bot2> <20260703214821.GHakguJTquox_L1X_E@fat_crate.local> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260703214821.GHakguJTquox_L1X_E@fat_crate.local> * Borislav Petkov wrote: > On Thu, Jul 02, 2026 at 10:15:54AM -0000, tip-bot2 for Juergen Gross wrote: > > diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c > > index 1fdcd69..c670fbb 100644 > > --- a/arch/x86/kernel/cpu/transmeta.c > > +++ b/arch/x86/kernel/cpu/transmeta.c > > @@ -24,7 +24,8 @@ static void early_init_transmeta(struct cpuinfo_x86 *c) > > > > static void init_transmeta(struct cpuinfo_x86 *c) > > { > > - unsigned int cap_mask, uk, max, dummy; > > + u64 msr; > > + unsigned int max, dummy; > > unsigned int cms_rev1, cms_rev2; > > unsigned int cpu_rev, cpu_freq = 0, cpu_flags, new_cpu_rev; > > char cpu_info[65]; > > The tip-tree preferred ordering of variable declarations at the > beginning of a function is reverse fir tree order:: While that's true, the style violation is a pre-existing condition in the current code: unsigned int cap_mask, uk, max, dummy; unsigned int cms_rev1, cms_rev2; unsigned int cpu_rev, cpu_freq = 0, cpu_flags, new_cpu_rev; char cpu_info[65]; ... and the best policy regarding API conversion patches like this is to keep the original style, to not mix several changes together, which only makes review harder. But I agree with fixing the style problems of course, but it should be done either in a preparatory patch, or in a followup patch. Either ordering is fine to me. Thanks, Ingo