From: Corey Minyard <cminyard@mvista.com>
To: Emmanuel Blot <emmanuel.blot@free.fr>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
qemu-devel@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@mailo.com>,
"Fabiano Rosas" <farosas@suse.de>,
"Laurent Vivier" <lvivier@redhat.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Jamin Lin" <jamin_lin@aspeedtech.com>,
"Kane Chen" <kane_chen@aspeedtech.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Alexander Hansen" <alexander.hansen@9elements.com>,
"William de Abreu Pinho" <williampinho@meta.com>,
"Emmanuel Blot" <eblot@meta.com>,
qemu-arm@nongnu.org
Subject: Re: [PATCH v5 6/8] hw/i2c: parent slaves created with i2c_slave_create_simple
Date: Fri, 17 Jul 2026 07:57:21 -0500 [thread overview]
Message-ID: <alomsclAchz2_bWy@mail.minyard.net> (raw)
In-Reply-To: <D5F0871C-4AC1-43D6-9BCD-C59A07236A1F@free.fr>
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On Thu, Jul 16, 2026 at 07:08:04PM +0200, Emmanuel Blot wrote:
>
>
> On 10 Jul 2026, at 18:05, Peter Maydell wrote:
>
> > On Wed, 1 Jul 2026 at 18:31, Emmanuel Blot <emmanuel.blot@free.fr> wrote:
> >>
> >> Slaves created with i2c_slave_create_simple() were left unparented and
> >> showed up under /machine/unattached with no stable QOM path. Add each
> >> slave as a QOM child of its bus, named after its I2C address, so it has
> >> a deterministic and addressable QOM path.
> >
> > Should devices on a bus be QOM children of the bus, though?
> > I would expect that they ought to be QOM children of e.g.
> > the SoC or machine that created them.
> >
> > Do we do this for other bus types, e.g. PCI ?
>
> If we do not want a I2C device to be a child of its bus, an alternative parent could be the master/controller of the bus. However as a controller may manage several buses, we need to add bus differentiator in the child name, such as bus_num:address.
>
> I do not think it makes more sense to have the I2C device to be a child of the SoC rather than its dedicated controller.
>
> On machines that are statically defined rather than composed from the command line (BMCs, complex SoC-based machines, …), all the I2C devices would appear as a “flat” list of devices, with sometimes many instances of the same I2C device type belonging to very different sub-domains of the machine they instrument and/or drive.
>
> I tend to think that using a flat schema would likely make use of QOM paths more difficult to observe and reach a device at run time: one would have to iterate the device and bus hierarchy rather than to use QOM path to access a device, or special care would be required for naming device instances. I was viewing the role of the QOM paths as a way to expose the machine device hierarchy as a comprehensive and non-ambiguous representation.
>
> What are the cons for using the device/bus hierarchy for simple buses such as SPI & I2C?
> Is there any drawback to use the device & bus hierarchy to assign a default/fallback QOM path to a device?
>
> Maybe it’s a matter of ownership? Neither the I2C. bus nor the I2C controller owns the device for sure.
Well, "own" doesn't have much of a meaning in this context. It's a
matter of how it's connected.
I agree with you philosophically. From a user's point of view, a
hierarchy is much more obvious. Otherwise you will have to create a
fake hierarchy with the names or you won't be able to find anything.
I looked at https://lore.kernel.org/qemu-devel/87se5scipx.fsf@pond.sub.org/
but not much came of that.
It would be ideal if the hierarchy was a natural part of the APIs that
register a device. If you put a device on an I2C bus, it becomes a
child of that I2C bus automatically.
However, corner cases exist. Multi-master I2C chips would have two
parent I2C busses connected to a single child I2C bus, for instance.
Anything multi-master would have this issue. Thinking about it some
more, a PHY might be on an MDIO bus but also connects to the main
ethernet interface. Lots of chips have SPI/I2C control interfaces but
them some other interface for passing data. A GPIO that enables a
chip but that chip is on a CAN bus interface.
So if you did something like this, you would need some sort of "multiple
inheritance" to cover the corner cases or you would have to live with
the inconsistency.
Device tree, for instance, has a strict hierarchy, but then has ways to
reference the other interfaces that can also control a device. IIRC
a PHY would sit on the MDIO bus for hierarchy and the ethernet device
has a reference that says "This is my PHY."
-corey
>
> Emmanuel.
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next prev parent reply other threads:[~2026-07-17 12:57 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-01 17:28 [PATCH v5 0/8] hw/sensor: Add new device emulation for TI ADC128D818 Emmanuel Blot
2026-07-01 17:28 ` [PATCH v5 1/8] hw/sensor: adc128d818: add 12-bit 8-channel ADC device Emmanuel Blot
2026-07-01 17:28 ` [PATCH v5 2/8] tests/qtest: adc128d818: add test harness and register access Emmanuel Blot
2026-07-01 17:28 ` [PATCH v5 3/8] tests/qtest: adc128d818: test voltage and temperature conversion Emmanuel Blot
2026-07-01 17:28 ` [PATCH v5 4/8] tests/qtest: adc128d818: test limit interrupts Emmanuel Blot
2026-07-01 17:28 ` [PATCH v5 5/8] tests/qtest: adc128d818: test operating modes and power control Emmanuel Blot
2026-07-01 17:28 ` [PATCH v5 6/8] hw/i2c: parent slaves created with i2c_slave_create_simple Emmanuel Blot
2026-07-06 7:14 ` Cédric Le Goater
2026-07-10 15:25 ` Markus Armbruster
2026-07-16 16:56 ` emmanuel.blot
2026-07-16 17:04 ` Cédric Le Goater
2026-07-10 16:05 ` Peter Maydell
2026-07-16 17:08 ` Emmanuel Blot
2026-07-17 12:57 ` Corey Minyard [this message]
2026-07-17 13:28 ` Peter Maydell
2026-07-17 14:03 ` emmanuel.blot
2026-07-01 17:28 ` [PATCH v5 7/8] hw/arm: anacapa: add ADC128D818 devices Emmanuel Blot
2026-07-01 17:28 ` [PATCH v5 8/8] test/functional: anacapa: test ADC128D818 Emmanuel Blot
2026-07-06 8:06 ` Cédric Le Goater
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