From mboxrd@z Thu Jan 1 00:00:00 1970 From: atull Subject: Re: [PATCH v12 3/6] fpga: add simple-fpga-bus Date: Wed, 28 Oct 2015 12:41:33 -0500 Message-ID: References: <1445983755-24007-1-git-send-email-atull@opensource.altera.com> <1445983755-24007-4-git-send-email-atull@opensource.altera.com> <20151028100714.GB7779@jcartwri.amer.corp.natinst.com> <20151028161859.GJ8245@jcartwri.amer.corp.natinst.com> Mime-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Return-path: In-Reply-To: Sender: linux-doc-owner@vger.kernel.org To: Moritz Fischer Cc: Josh Cartwright , Greg KH , Michal Simek , Michal Simek , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Jonathan Corbet , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Pantelis Antoniou , Alan Tull , "dinguyen@opensource.altera.com" List-Id: devicetree@vger.kernel.org On Wed, 28 Oct 2015, atull wrote: > On Wed, 28 Oct 2015, Moritz Fischer wrote: > > > On Wed, Oct 28, 2015 at 9:18 AM, Josh Cartwright wrote: > > > On Wed, Oct 28, 2015 at 08:37:51AM -0700, Moritz Fischer wrote: > > >> On Wed, Oct 28, 2015 at 3:07 AM, Josh Cartwright wrote: > > >> > On Tue, Oct 27, 2015 at 05:09:12PM -0500, atull@opensource.altera.com wrote: > > >> >> From: Alan Tull > > >> >> > > >> >> The Simple FPGA bus uses the FPGA Manager Framework and the > > >> >> FPGA Bridge Framework to provide a manufactorer-agnostic > > >> >> interface for reprogramming FPGAs that is Device Tree > > >> >> Overlays-based. > > >> > > > >> > Do you intend the "simple-fpga-bus" to be used on Zynq as well? The > > >> > whole concept of the socfpga's "FPGA Bridge" doesn't map to the Zynq at > > >> > all, from what I can tell. > > >> > > >> For Zynq the zynq-fpga driver takes care of the level shifters on full > > >> reconfiguration, > > >> and doesn't for partial reconfiguration. Now depending on which parts > > >> of the fabric > > >> are partial reconfigured (say AXI masters), one might run into issues > > >> with a setup like that. > > >> > > >> My first plan was to counter that by using zynq-reset to hold the > > >> reset high during > > >> reconfiguration of that part of the FPGA. > > >> > > >> I'm happy to rethink that part and maybe redo the level shifters and > > >> resets together in a bridge > > >> driver under devicetree control gives finer grained control. > > > > > > There is already a framework which is used to describe and manipulate > > > level shifting/other IO properties, and that is pinctrl, and if we > > > wanted to use an appropriate abstraction, I think pinctrl would be the > > > best bet. > > > > Alright, I'll investigate that. Again, for the non-partial reconfig > > case I'm happy > > with the behavior as implemented, for the partial reconfig I just > > haven't run into > > issues with not dealing with the level shifters. > > Are you suggesting pinctrl instead of introducing a FPGA Bridge Framework? > If it fits, that's great. Steffen is urging us to include reconfiguring > width of the bridge so I'm trying to figure how and if that all fits in > here. > Hi Josh, I don't think pinctrl is a good match here or even could be made to do what we need here. Simple FPGA Bus needs, at minimum, an API to call to enable/disable data through a bridge to protect the processor bus from spurious data while the FPGA is being programmed. Alan From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755625AbbJ1Rsw (ORCPT ); Wed, 28 Oct 2015 13:48:52 -0400 Received: from mail-bn1bon0064.outbound.protection.outlook.com ([157.56.111.64]:43952 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755391AbbJ1Rss (ORCPT ); Wed, 28 Oct 2015 13:48:48 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.227) smtp.mailfrom=opensource.altera.com; lwn.net; dkim=none (message not signed) header.d=none;lwn.net; dmarc=none action=none header.from=opensource.altera.com; Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=atull@opensource.altera.com; Date: Wed, 28 Oct 2015 12:41:33 -0500 From: atull X-X-Sender: atull@linuxheads99 To: Moritz Fischer CC: Josh Cartwright , Greg KH , Michal Simek , Michal Simek , "Rob Herring" , Pawel Moll , Mark Rutland , Ian Campbell , "Kumar Gala" , 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X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a;Ip=[66.35.236.227];Helo=[sj-itexedge03.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR03MB1498 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 28 Oct 2015, atull wrote: > On Wed, 28 Oct 2015, Moritz Fischer wrote: > > > On Wed, Oct 28, 2015 at 9:18 AM, Josh Cartwright wrote: > > > On Wed, Oct 28, 2015 at 08:37:51AM -0700, Moritz Fischer wrote: > > >> On Wed, Oct 28, 2015 at 3:07 AM, Josh Cartwright wrote: > > >> > On Tue, Oct 27, 2015 at 05:09:12PM -0500, atull@opensource.altera.com wrote: > > >> >> From: Alan Tull > > >> >> > > >> >> The Simple FPGA bus uses the FPGA Manager Framework and the > > >> >> FPGA Bridge Framework to provide a manufactorer-agnostic > > >> >> interface for reprogramming FPGAs that is Device Tree > > >> >> Overlays-based. > > >> > > > >> > Do you intend the "simple-fpga-bus" to be used on Zynq as well? The > > >> > whole concept of the socfpga's "FPGA Bridge" doesn't map to the Zynq at > > >> > all, from what I can tell. > > >> > > >> For Zynq the zynq-fpga driver takes care of the level shifters on full > > >> reconfiguration, > > >> and doesn't for partial reconfiguration. Now depending on which parts > > >> of the fabric > > >> are partial reconfigured (say AXI masters), one might run into issues > > >> with a setup like that. > > >> > > >> My first plan was to counter that by using zynq-reset to hold the > > >> reset high during > > >> reconfiguration of that part of the FPGA. > > >> > > >> I'm happy to rethink that part and maybe redo the level shifters and > > >> resets together in a bridge > > >> driver under devicetree control gives finer grained control. > > > > > > There is already a framework which is used to describe and manipulate > > > level shifting/other IO properties, and that is pinctrl, and if we > > > wanted to use an appropriate abstraction, I think pinctrl would be the > > > best bet. > > > > Alright, I'll investigate that. Again, for the non-partial reconfig > > case I'm happy > > with the behavior as implemented, for the partial reconfig I just > > haven't run into > > issues with not dealing with the level shifters. > > Are you suggesting pinctrl instead of introducing a FPGA Bridge Framework? > If it fits, that's great. Steffen is urging us to include reconfiguring > width of the bridge so I'm trying to figure how and if that all fits in > here. > Hi Josh, I don't think pinctrl is a good match here or even could be made to do what we need here. Simple FPGA Bus needs, at minimum, an API to call to enable/disable data through a bridge to protect the processor bus from spurious data while the FPGA is being programmed. Alan