From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 8 Nov 2016 18:53:02 +0100 (CET) From: Thomas Gleixner Subject: Re: [PATCH v9 7/7] KVM: x86: virtualize cpuid faulting In-Reply-To: Message-ID: References: <20161106205742.4042-1-khuey@kylehuey.com> <20161106205742.4042-8-khuey@kylehuey.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org To: Kyle Huey Cc: David Matlack , Robert O'Callahan , Andy Lutomirski , Ingo Molnar , "H. Peter Anvin" , X86 ML , Paolo Bonzini , =?ISO-8859-2?Q?Radim_Kr=E8m=E1=F8?= , Jeff Dike , Richard Weinberger , Alexander Viro , Shuah Khan , Dave Hansen , Borislav Petkov , Peter Zijlstra , Boris Ostrovsky , Len Brown , "Rafael J. Wysocki" , Dmitry Safonov , "linux-kernel@vger.kernel.org" , "open list:USER-MODE LINUX (UML)" , "open list:USER-MODE LINUX (UML)" , "open list:FILESYSTEMS (VFS and infrastructure)" , "open list:KERNEL SELFTEST FRAMEWORK" , kvm list List-ID: On Tue, 8 Nov 2016, Kyle Huey wrote: > > It will simplify the MSR get/set code, and make it easier to plumb > > support for new bits in these MSRs. > > I'm inclined to do this for MSR_PLATFORM_INFO but not > MSR_MISC_FEATURES_ENABLES. The former actually has other bits, and > isn't used outside the msr handling code (yet, anyways). > MSR_MISC_FEATURES_ENABLES doesn't have any other bits (it's actually > not documented by Intel at all outside of that virtualization paper) > and after masking bits in cpuid.c or adding a helper function the > complexity would be a wash at best. The feature MSR is also used for enabling ring3 MWAIT, which is obviously not documented either. So there is more stuff coming along.... Thanks, tglx From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Gleixner Subject: Re: [PATCH v9 7/7] KVM: x86: virtualize cpuid faulting Date: Tue, 8 Nov 2016 18:53:02 +0100 (CET) Message-ID: References: <20161106205742.4042-1-khuey@kylehuey.com> <20161106205742.4042-8-khuey@kylehuey.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Cc: David Matlack , Robert O'Callahan , Andy Lutomirski , Ingo Molnar , "H. Peter Anvin" , X86 ML , Paolo Bonzini , =?ISO-8859-2?Q?Radim_Kr=E8m=E1=F8?= , Jeff Dike , Richard Weinberger , Alexander Viro , Shuah Khan , Dave Hansen , Borislav Petkov , Peter Zijlstra , Boris Ostrovsky , Len Brown , "Rafael J. Wysocki" , Dmitry Safonov , "linux-kernel@vger.kernel.org To: Kyle Huey Return-path: Received: from Galois.linutronix.de ([146.0.238.70]:55723 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752029AbcKHR5O (ORCPT ); Tue, 8 Nov 2016 12:57:14 -0500 In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: On Tue, 8 Nov 2016, Kyle Huey wrote: > > It will simplify the MSR get/set code, and make it easier to plumb > > support for new bits in these MSRs. > > I'm inclined to do this for MSR_PLATFORM_INFO but not > MSR_MISC_FEATURES_ENABLES. The former actually has other bits, and > isn't used outside the msr handling code (yet, anyways). > MSR_MISC_FEATURES_ENABLES doesn't have any other bits (it's actually > not documented by Intel at all outside of that virtualization paper) > and after masking bits in cpuid.c or adding a helper function the > complexity would be a wash at best. The feature MSR is also used for enabling ring3 MWAIT, which is obviously not documented either. So there is more stuff coming along.... Thanks, tglx