From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>,
Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH v3] MIPS: Alchemy: fix wait function
Date: Mon, 10 Jun 2013 18:17:24 +0100 (BST) [thread overview]
Message-ID: <alpine.LFD.2.03.1306101816150.18329@linux-mips.org> (raw)
In-Reply-To: <1370722541-25407-1-git-send-email-manuel.lauss@gmail.com>
On Sat, 8 Jun 2013, Manuel Lauss wrote:
> diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
> index 3b09b88..0c655de 100644
> --- a/arch/mips/kernel/idle.c
> +++ b/arch/mips/kernel/idle.c
> @@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
> }
>
> /*
> - * The Au1xxx wait is available only if using 32khz counter or
> - * external timer source, but specifically not CP0 Counter.
> - * alchemy/common/time.c may override cpu_wait!
> + * Au1 'wait' is only useful when the 32kHz counter is used as timer,
> + * since coreclock (and the cp0 counter) stops upon executing it. Only an
> + * interrupt can wake it, so they must be enabled before entering idle modes.
> */
> static void au1k_wait(void)
> {
> + unsigned long c0status = read_c0_status() | 1; /* irqs on */
> +
> __asm__(
> " .set mips3 \n"
> " cache 0x14, 0(%0) \n"
> " cache 0x14, 32(%0) \n"
> " sync \n"
> - " nop \n"
> + " mtc0 %1, $12 \n" /* wr c0status */
> " wait \n"
> " nop \n"
> " nop \n"
> " nop \n"
> " nop \n"
> " .set mips0 \n"
> - : : "r" (au1k_wait));
> - local_irq_enable();
> + : : "r" (au1k_wait), "r" (c0status));
> }
>
> static int __initdata nowait;
Not exacly what I had in mind, but this looks good to me too. :)
Acked-by: Maciej W. Rozycki <macro@linux-mips.org>
Maciej
prev parent reply other threads:[~2013-06-10 17:17 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-08 20:15 [PATCH v3] MIPS: Alchemy: fix wait function Manuel Lauss
2013-06-10 15:53 ` Ralf Baechle
2013-06-10 17:17 ` Maciej W. Rozycki [this message]
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