From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FB4F33689A for ; Thu, 23 Jul 2026 08:02:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784793777; cv=none; b=iJYICRa4RCGEOYuiaYMah3IS40TGsuGrBRNH067cDQHiaPVssuy8BB9zUYQ1bx/382sQT52MQvVDHjaF7wY1SgAV7MCL5HidvMJH7uF4epe+Qq3HKy0qx1j3iriFdueP+CQwpjWT1RVgbfNB5XBLLUNahpqOtT/fHlJEtKAl7uI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784793777; c=relaxed/simple; bh=oKR3bnzRbyNxjZyu8oC7IQyNdCU5LUeUe+7pu7ukq28=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=IpNrB8D6YpaIo77SmdsrpbhPuB7NyLJC6u8VLCI/7b1jy12zf2B8xvXcWjC9BGpZj3hTUqerpcxqhmB7jhsjAv2MNf7f8auoVIPiVhKdosgL3Uu/JUqawqNC3kJTo5qAmGgmU5qD08oemBpg07RmJUVWWIX9+7fqDw/hnyofHQM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GnBOehij; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GnBOehij" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F8E21F000E9; Thu, 23 Jul 2026 08:02:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784793775; bh=2c+OwzlZN254ioXALFTMwXnVzAJAGqLI1hoyO6xvnPY=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=GnBOehijO3SkBxiSzUjqNvqZZegjpsXKJ47llVWGea6ZeWeu2fybTGPldzunFbwjt c7bawmTiquPkSvt94zrX2CenIme2EMIvFF7jcfbeSQbCst/OqbLHpiv5JnubghC/Im +JoiXYZ1ArN2t9dOS70Dx9d5z8AYir5FG0N3yOLMPhVhzvZUbUzvCq4qWKI/b7xjb2 lyvts9ZlkD8Ng3s0Ypc8TKpBP+bjG7Y1J8PRqXm1WC2cKCBGlFAYOukXtTR52uD72q FqaBAXZ9GYGncIcV1rY3CR/ioeotpv08bWkqzaMqhagPvmYbsJPenA3XxPgxjn8m98 MlRGXRwbP12nQ== Date: Thu, 23 Jul 2026 10:02:51 +0200 From: Ingo Molnar To: "Naveen N Rao (AMD)" Cc: Borislav Petkov , Dave Hansen , linux-kernel@vger.kernel.org, x86@kernel.org, Thomas Gleixner , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" Subject: Re: [PATCH v4 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Message-ID: References: <2d18caf834a2e66e4c6787e3c3058fd6bb6e5d3e.1784785046.git.naveen@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2d18caf834a2e66e4c6787e3c3058fd6bb6e5d3e.1784785046.git.naveen@kernel.org> * Naveen N Rao (AMD) wrote: > For AMD family 0x10, EILVT offsets are not assigned by BIOS and is > instead assigned by picking the next available EILVT offset. Use the > maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than > an arbitrary maximum EILVT count when looking for the next available > EILVT offset. > > Signed-off-by: Naveen N Rao (AMD) > Tested-by: Manali Shukla > --- > arch/x86/events/amd/ibs.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c > index 3531f9c23b8c..555912ac520f 100644 > --- a/arch/x86/events/amd/ibs.c > +++ b/arch/x86/events/amd/ibs.c > @@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void) > > preempt_disable(); > /* find the next free available EILVT entry, skip offset 0 */ > - for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) { > + for (offset = 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { Nit: s/APIC_EILVT_NR_AMD_10H /APIC_EILVT_NR_MAX_AMD_10H to make it clear at first sight that this is a (family specific) maximum, not some default count or other random value. Thanks, Ingo