From: Varadarajan Narayanan via U-Boot <u-boot@lists.u-boot-project.org>
To: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Cc: Sumit Garg <sumit.garg@kernel.org>,
u-boot-qcom@groups.io, u-boot@lists.u-boot-project.org,
Lukasz Majewski <lukma@denx.de>,
Casey Connolly <casey.connolly@linaro.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Tom Rini <trini@konsulko.com>, Ajit Singh <blfizzyy@gmail.com>,
Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Subject: Re: [PATCH 1/3] clk: qcom: sa8775p: use GATE_CLK_POLLED for CBCR-backed gate clocks
Date: Thu, 23 Jul 2026 14:05:12 +0530 [thread overview]
Message-ID: <amHSQIp9C5sxGxpW@hu-varada-blr.qualcomm.com> (raw)
In-Reply-To: <20260723-clk_gate-v1-1-9549cad4d097@oss.qualcomm.com>
On Thu, Jul 23, 2026 at 12:09:46PM +0530, Balaji Selvanathan via U-Boot wrote:
> Convert the USB3 and UFS PHY reference clocks in the sa8775p gate
> clock table from GATE_CLK() to GATE_CLK_POLLED(), so their enable
> status is polled against the per-clock CBCR register instead of
> assuming the enable write completed immediately.
>
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
next prev parent reply other threads:[~2026-07-23 8:35 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 6:39 [PATCH 0/3] clk: qcom: use GATE_CLK_POLLED for CBCR-backed gate clocks Balaji Selvanathan via U-Boot
2026-07-23 6:39 ` [PATCH 1/3] clk: qcom: sa8775p: " Balaji Selvanathan via U-Boot
2026-07-23 8:35 ` Varadarajan Narayanan via U-Boot [this message]
2026-07-23 6:39 ` [PATCH 2/3] clk: qcom: sc7280: " Balaji Selvanathan via U-Boot
2026-07-23 8:35 ` Varadarajan Narayanan via U-Boot
2026-07-23 6:39 ` [PATCH 3/3] clk: qcom: qcs615: " Balaji Selvanathan via U-Boot
2026-07-23 8:36 ` Varadarajan Narayanan via U-Boot
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