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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-907baa27cf1sm48281876d6.46.2026.07.23.09.42.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 09:42:55 -0700 (PDT) Date: Thu, 23 Jul 2026 12:42:54 -0400 From: Brian Masney To: joakim.zhang@cixtech.com Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, cix-kernel-upstream@cixtech.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v11 2/4] clk: cix: add sky1 audss clock controller Message-ID: References: <20260723090808.1727598-1-joakim.zhang@cixtech.com> <20260723090808.1727598-3-joakim.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260723090808.1727598-3-joakim.zhang@cixtech.com> User-Agent: Mutt/2.4.0 (2026-06-19) Hi Joakim, There's one question from Sashiko that I don't see where you answered that seems to be legit. On Thu, Jul 23, 2026 at 05:08:06PM +0800, joakim.zhang@cixtech.com wrote: > From: Joakim Zhang > > Add a platform driver for the Cix Sky1 AUDSS CRU. The driver maps > the CRU registers and registers mux, divider and gate clocks for > DSP, SRAM, HDA, DMAC, I2S, mailbox, watchdog and timer blocks. > > Four SoC-level audio reference clocks are enabled as inputs to the > internal clock tree. The driver releases the AUDSS NOC reset, enables > runtime PM and instantiates the auxiliary reset device. > > Signed-off-by: Joakim Zhang [snip] > +static int __maybe_unused sky1_audss_clk_runtime_resume(struct device *dev) > +{ > + struct sky1_audss_clks_priv *priv = dev_get_drvdata(dev); > + const struct sky1_audss_clks_devtype_data *devtype_data = priv->devtype_data; > + unsigned long flags; > + int i, ret; > + > + ret = sky1_audss_clks_enable(priv); >From Sashiko: [Severity: High] Could this result in a deadlock? When a consumer calls clk_prepare on an audss clock, CCF acquires the global prepare_lock mutex and may call pm_runtime_resume_and_get. This triggers sky1_audss_clk_runtime_resume, which calls sky1_audss_clks_enable. Since sky1_audss_clks_enable executes clk_prepare_enable, it will attempt to acquire the non-recursive prepare_lock again. I found drivers/clk/samsung/clk-exynos-audss.c that is similar to your driver and it calls clk_prepare_enable() in probe. I'm not concerned about the other feedback from Sashiko. Brian