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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?ZL53NH3Oz7MyMatgbA6Hq3wfxreo4NjNNUBUl5wERIOqwiXx/EIXwF62ozEt?= =?us-ascii?Q?RnOUmpd8s9srjtJGVr1ZxSf+mBuOdZnCM9EvNTNdokqZHbs1qGni7kJZCW1f?= =?us-ascii?Q?MYZ8a4O8b8bKNtla/gQgi1xFWOQ/k4ClzAfHtisc/sb78zh9Kj4iiqZ56CFY?= =?us-ascii?Q?OM3UDw7KZnTIOoKMVMAtv3Q+Tf1DD/HarbJf//8sfTZIxRFlTff1hvLQKJKP?= =?us-ascii?Q?MAtqCgPKic2MbhcN2bmvNgyQerZIDwUvHwrt4YsjbTNwlgrByCS5CnGyJcqV?= =?us-ascii?Q?VOMBjHcRXGjpW0KS0pmSfcviawCcuo8gTE2fOl3EYAgZUMefjVm12/k0l4IU?= =?us-ascii?Q?cEOkLUxKW2brPFl5pYKH8IfdLRLgsIS9G2RnmrcZ2QU6zS7Y4bNiEk+f22VG?= =?us-ascii?Q?FxMfDeWbw3vfZGxlEQ9q0cO2jU2uTf/yuUuLHUpIy+0+h/+2KlejpfhtBIp4?= =?us-ascii?Q?RWLx4qT3+5f7RSuQwOr8iK4Hu4/szalDiuxCvuR+J8YIezIJ7XIksP3v25EP?= =?us-ascii?Q?pxz3JmzsKiq5TexY99z/Iz/LtFUVbF0Tt+1dahzzxlK7v6dNIqU775d/Dlj3?= =?us-ascii?Q?1o7kDgsWWJBAOe2rTCJZuXNggtD8GysYNvP59Mt4sgN60C4+hn/plQ4pQY/W?= =?us-ascii?Q?uImLsROFFFrNGObTl+dAM6MSDNLd8eA+Gm0/qxBbLfT2jiDzpkQIYb1XhnUD?= =?us-ascii?Q?n3hV8ZIloT32JrwHutaNVWUGpthDmvEBV/XjYDGYu+GXL1AUc3NKfOhUy8qO?= =?us-ascii?Q?uAI9dCHrMAiOASGNGVE5OY0K5JKkPrhqOSxm1N9Gi3tUlVbAeRG1qC8tnXwS?= =?us-ascii?Q?r0wXceYRnIy2p8twkmEBWlYh9kkq9RXbc2tZloZ/+0XbAdZpAitFic0/JPz6?= =?us-ascii?Q?O1tHaQNHZYvdRsCxfYztD8frUdq3pKiw2fddOvyD8aAOXMZ1r9+1MyofwzBA?= =?us-ascii?Q?1vR+1+lfGnJ5PBUP3KYwj6Am7ag8hVQugNoLwsrzfi2IVtC+agAZRnCL2rYX?= =?us-ascii?Q?K685rUWbD1e34m7/wgp91DsQLmkMRHM6VLjgmxNT4bGbw7bz7Uun554vAxoq?= =?us-ascii?Q?pHWJGgvV8G+R+sLMLEdGO4Dgl4UnoCoF4A5eIIQzSWzlmSCmWuxFy3oanHbc?= =?us-ascii?Q?thOOYCgT7fmzp1VOIVKBO96HmgADcULDSPgGp8WUdRVqnioYO8OA5IiQnN3k?= =?us-ascii?Q?axDoFHcEXuWfijoN+KXcUWO0FXJcEXX91PPNnK+CJlmdtSBVooFXq6jNhJey?= =?us-ascii?Q?tXzfKheTKuvz2ifDtCalMODdJc9iBeolWXoNLHCLH+Fr4OwGdj7maDDgPS2v?= =?us-ascii?Q?dzUhKCx7ZDeN5uWdR8CF5xyQ71I6kg6XstVM9v932lxEACPFqg0S77wDWr9e?= =?us-ascii?Q?W+rvN3JBpyLDNT6vq3Z94h2wkKi+8KoZ/EIQdM7359S9OaJrNbDCOVwqQQ22?= =?us-ascii?Q?RGXGluQpi28GF1PloqpdwWShxh19cCuR4vvW7WdoUELNkKP89gLZl0m4bop8?= =?us-ascii?Q?qitaljy+9GbUJWuJEHKhtlmMirbfYq7B89ByHeF405eOl8lvhpXDOBT6IrS8?= =?us-ascii?Q?nDUrZs80itPdL16fD/F7kd0KLNa7Y0/kdCeWmWipdDb3PFL4AAcd8Odezes6?= =?us-ascii?Q?qRJSoD2NK2OPW9XzIGxjTXEeXRob9t0fLCjgJbyLCwyp+bJcx+f4gZTKslET?= =?us-ascii?Q?1XjLS7BlsvMZn3yX0uf0KFcs0vL1HVUjlDye1J89a6+J3hGg?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e817a4c7-193e-4204-4463-08dee9951b19 X-MS-Exchange-CrossTenant-AuthSource: LV3PR12MB9356.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2026 15:06:15.0641 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kn61DkIoI5AwmZRaoe4TtYKGM4kcN8AAZfNv/Pb9mboGh4teM3VtIvRjjimxGe//BYhioXRzQ+LRdtWeVqdMLA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6150 On Thu, Jul 23, 2026 at 05:59:09PM +0900, Eliot Courtney wrote: > Add support for reserving of ranges of IDs, with a usage in nova-core > for channel IDs. This entails adding bindings for the C bitmap > API for ranges of bits, then users of that in `IdPool`, and finally a > user of `IdPool` in nova-core, `ChannelIdPool`. > > Channel ID tracking is needed for allotting ranges of channel IDs to > vGPU guests, and later for regular host channel ID reservation. > nova-core needs allocation of a contiguous sequence of IDs with a > specific length and sometimes a specific alignment [1]. > > About the tradeoffs between different data structures: > - IDA/xarray do not support allocating a contiguous sequence of IDs > (ida_alloc_range() allocates a single ID within a range, not a contiguous > sequence). > - A maple tree works, but is not as good a fit. The ID space is small > (limited to 2048) and aligned allocation needs an alloc_range()+erase() retry > loop (plus a Mutex around it, or new mas_empty_area() bindings) that > essentially reimplements bitmap_find_next_zero_area(). See the maple tree > version at [2]. For 2048 IDs a bitmap is also considerably faster and smaller > [3]. > - The bitmap API natively supports aligned contiguous area allocation > (bitmap_find_next_zero_area()). > > This is based on drm-rust-next. > > [1]: https://lore.kernel.org/all/84bc8bd2-e292-4b84-9580-a1b5df4c5bdc@nvidia.com/ > [2]: https://lore.kernel.org/all/20260710-chid-maple-v1-1-4ee869055268@nvidia.com/ > [3]: https://lore.kernel.org/all/20260717053241.916441-1-ynorov@nvidia.com/ If you refer my test, I'd like to make sure you've reviewed it and tested in your environment. Please send the appropriate tags. Also, would you like to add it to your series? I can to move it myself, but I can defer it to you if you prefer. Thanks, Yury > Signed-off-by: Eliot Courtney > --- > Changes in v2: > - Collected Alice's Reviewed-by on patch 1. > - Address Yury's comments w.r.t. using __bitmap_set etc directly. > - Address Yury's comments w.r.t. following the C names > - Additionally check for an overflow case that causes a hang > - Added more info to cover letter + patch 4 w.r.t. channel ID allottment > requirements > - Add align parameter to ChannelIdPool::alloc_area() plus an aligned > allocation test > - Add missing INVARIANT comment when constructing UnusedArea > - Link to v1: > https://patch.msgid.link/20260703-chid-v1-0-84fe8259e46e@nvidia.com > > --- > Eliot Courtney (4): > rust: bitmap: use function-level cfg on kunit test > rust: bitmap: add contiguous area operations > rust: id_pool: add contiguous area allocation > gpu: nova-core: add ChannelIdPool > > drivers/gpu/nova-core/gpu.rs | 2 + > drivers/gpu/nova-core/gpu/channel.rs | 182 ++++++++++++++++++++++++++ > rust/kernel/bitmap.rs | 242 +++++++++++++++++++++++++++++++++-- > rust/kernel/id_pool.rs | 69 ++++++++++ > 4 files changed, 481 insertions(+), 14 deletions(-) > --- > base-commit: 71d4e7233f235871b13553e504e591ace6b54373 > change-id: 20260608-chid-18fa943c6d6c > > Best regards, > -- > Eliot Courtney