From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E326AC531D0 for ; Mon, 27 Jul 2026 09:15:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fpab5oMt1IkFgVDltEsVt7Vx38Yr/w/n6RKd5z9Xmz8=; b=CZ2UNl0VubYmwgF67JuAdzVrgK 0Z8K+qxEa41MtrAGQ3/AIIcZFp6hFhyHcqzd/H/StQxVlREavKOUH8n+z5tpWPLM4z3Bai8/KMtOn O8esUreNTLpb84g+Q+WgYSNmSRZs4Oa7A8a5MO+uokAVUI83hTkHc3MMTiFOx5fAv3OdOGgxm+vui 7urBt8js57Q8LFJaboqNKxctjPwl5v1ZxoZ+/VLceUZQB3RDW2DJ7+mfD+eH+63jtB7VpbAk75baQ 8gqxAMqV2bkD9jPQa70tlofFP+RkAeR6tzxUIiwdYZmykuIHzmmNf+q3w3Vh74qJpDPoFrMlYUb5n xfyFChCw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1woHQL-00000002IeS-1M7L; Mon, 27 Jul 2026 09:15:01 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1woHQJ-00000002Ie5-2NI8 for linux-mediatek@lists.infradead.org; Mon, 27 Jul 2026 09:15:00 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 92F80601DE; Mon, 27 Jul 2026 09:14:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7EADF1F000E9; Mon, 27 Jul 2026 09:14:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785143698; bh=fpab5oMt1IkFgVDltEsVt7Vx38Yr/w/n6RKd5z9Xmz8=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=BdSnycWs8M3n0VFk1j++5MVntlI0W6/Z6f6UuNkiWhDac6aVi+2oYG36VMk9SacD5 xFRmnifzXeRxxM/bp0Q6jiJw7YGiMJ0W9w9OxKsIzWKQJMEhgqdJb5iR7ESxcwpd9s 1Umw2TkDfEG9jQ/ywjb7JhZUv/Lj3Hq3Ozkr9iTDSelujWuL0cmMSCa93RbHCDRzvw OySi/HYRaoJw8l77fwmT95C0TPBKHKwsmSLpCDWBXmuNDQPWb7XaWBZKM8KB+Ou5yy wbXI+sWIQRWEl3S//TducAhgloMN81bpQo+VoYZE5BGme8dTju3oo+cpjji9wtLa74 CaERyPkChmvvA== Date: Mon, 27 Jul 2026 11:14:54 +0200 From: Lorenzo Bianconi To: Mikhail Kshevetskiy Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Christian Marangi , Benjamin Larsson , AngeloGioacchino Del Regno , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Markus Gothe , Matheus Sampaio Queiroga Subject: Re: [PATCH v7 20/34] pinctrl: airoha: split driver on shared code and SoC specific drivers Message-ID: References: <20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu> <20260727074234.3761170-21-mikhail.kshevetskiy@iopsys.eu> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="bXde1pkZXIZW6GKB" Content-Disposition: inline In-Reply-To: <20260727074234.3761170-21-mikhail.kshevetskiy@iopsys.eu> X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org --bXde1pkZXIZW6GKB Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable > Split combined an7581/an7583 source file on a > * shared pinctrl code (pinctrl-airoha.c) > * an7581 specific pinctrl driver (pinctrl-an7581.c) > * an7583 specific pinctrl driver (pinctrl-an7583.c) I do not think we can have 7581 and 7583 chips at the same time on a given board so I guess we can avoid creating a dedicated module for the common co= de. I guess we can just create a library we can compile in. What do yout think? Regards, Lorenzo >=20 > Ininialization code was adapted a bit to work properly for shared > and SoC specific cases. >=20 > Signed-off-by: Mikhail Kshevetskiy > --- > drivers/pinctrl/airoha/Kconfig | 24 +- > drivers/pinctrl/airoha/Makefile | 5 + > drivers/pinctrl/airoha/airoha-common.h | 5 + > drivers/pinctrl/airoha/pinctrl-airoha.c | 2382 +---------------------- > drivers/pinctrl/airoha/pinctrl-an7581.c | 1486 ++++++++++++++ > drivers/pinctrl/airoha/pinctrl-an7583.c | 1456 ++++++++++++++ > 6 files changed, 2984 insertions(+), 2374 deletions(-) > create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c > create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c >=20 > diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kcon= fig > index 03adaeae8fc3a..dae6608bc72dd 100644 > --- a/drivers/pinctrl/airoha/Kconfig > +++ b/drivers/pinctrl/airoha/Kconfig > @@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers" > depends on ARCH_AIROHA || COMPILE_TEST > =20 > config PINCTRL_AIROHA > - tristate "Airoha EN7581 pin control" > + tristate "Airoha pin control" > depends on OF > - depends on ARM64 || COMPILE_TEST > + depends on ARCH_AIROHA || COMPILE_TEST > select PINMUX > select GENERIC_PINCONF > select GENERIC_PINCTRL_GROUPS > @@ -13,8 +13,26 @@ config PINCTRL_AIROHA > select GPIOLIB > select GPIOLIB_IRQCHIP > select REGMAP_MMIO > + imply PINCTRL_AIROHA_AN7581 > + imply PINCTRL_AIROHA_AN7583 > + help > + Shared pin controller and gpio driver code for different > + Airoha SoCs. > + > +config PINCTRL_AIROHA_AN7581 > + tristate "AN7581 pinctrl" > + depends on ARM64 || COMPILE_TEST > + depends on PINCTRL_AIROHA > + help > + Say yes here to support pin controller and gpio driver > + on Airoha AN7581, AN7566, AN7551 and other compatible SoCs. > + > +config PINCTRL_AIROHA_AN7583 > + tristate "AN7583 pinctrl" > + depends on ARM64 || COMPILE_TEST > + depends on PINCTRL_AIROHA > help > Say yes here to support pin controller and gpio driver > - on Airoha EN7581 SoC. > + on Airoha AN7583, AN7553, AN7567 and other compatible SoCs. > =20 > endmenu > diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Mak= efile > index a25b744dd7a8a..cfd68c45ae0f0 100644 > --- a/drivers/pinctrl/airoha/Makefile > +++ b/drivers/pinctrl/airoha/Makefile > @@ -1,3 +1,8 @@ > # SPDX-License-Identifier: GPL-2.0 > =20 > +# shared code > obj-$(CONFIG_PINCTRL_AIROHA) +=3D pinctrl-airoha.o > + > +# SoC drivers > +obj-$(CONFIG_PINCTRL_AIROHA_AN7581) +=3D pinctrl-an7581.o > +obj-$(CONFIG_PINCTRL_AIROHA_AN7583) +=3D pinctrl-an7583.o > diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/air= oha/airoha-common.h > index 40d7e515c09eb..f73e90ca860f4 100644 > --- a/drivers/pinctrl/airoha/airoha-common.h > +++ b/drivers/pinctrl/airoha/airoha-common.h > @@ -148,9 +148,12 @@ struct airoha_pinctrl { > struct regmap *regmap; > =20 > struct airoha_pinctrl_gpiochip gpiochip; > + struct irq_chip gpio_irq_chip; > }; > =20 > struct airoha_pinctrl_match_data { > + const char *pinctrl_name; > + struct module *pinctrl_owner; > const struct pinctrl_pin_desc *pins; > const unsigned int num_pins; > const struct pingroup *grps; > @@ -160,4 +163,6 @@ struct airoha_pinctrl_match_data { > const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_= MAX]; > }; > =20 > +int airoha_pinctrl_probe(struct platform_device *pdev); > + > #endif > diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/ai= roha/pinctrl-airoha.c > index f42631afc05d3..a46596eb1493b 100644 > --- a/drivers/pinctrl/airoha/pinctrl-airoha.c > +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c > @@ -7,365 +7,6 @@ > =20 > #include "airoha-common.h" > =20 > -/* MUX */ > -#define REG_GPIO_2ND_I2C_MODE 0x0214 > -#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14) > -#define GPIO_I2C_MASTER_MODE_MODE BIT(13) > -#define GPIO_I2S_MODE_MASK BIT(12) > -#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) > -#define GPIO_LAN3_LED1_MODE_MASK BIT(10) > -#define GPIO_LAN3_LED0_MODE_MASK BIT(9) > -#define GPIO_LAN2_LED1_MODE_MASK BIT(8) > -#define GPIO_LAN2_LED0_MODE_MASK BIT(7) > -#define GPIO_LAN1_LED1_MODE_MASK BIT(6) > -#define GPIO_LAN1_LED0_MODE_MASK BIT(5) > -#define GPIO_LAN0_LED1_MODE_MASK BIT(4) > -#define GPIO_LAN0_LED0_MODE_MASK BIT(3) > -#define PON_TOD_1PPS_MODE_MASK BIT(2) > -#define GSW_TOD_1PPS_MODE_MASK BIT(1) > -#define GPIO_2ND_I2C_MODE_MASK BIT(0) > - > -#define REG_GPIO_SPI_CS1_MODE 0x0218 > -#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) > -#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) > -#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) > -#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) > -#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) > -#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) > -#define GPIO_PCM_SPI_MODE_MASK BIT(16) > -#define GPIO_PCM2_MODE_MASK BIT(13) > -#define GPIO_PCM1_MODE_MASK BIT(12) > -#define GPIO_PCM_INT_MODE_MASK BIT(9) > -#define GPIO_PCM_RESET_MODE_MASK BIT(8) > -#define GPIO_SPI_QUAD_MODE_MASK BIT(4) > -#define GPIO_SPI_CS4_MODE_MASK BIT(3) > -#define GPIO_SPI_CS3_MODE_MASK BIT(2) > -#define GPIO_SPI_CS2_MODE_MASK BIT(1) > -#define GPIO_SPI_CS1_MODE_MASK BIT(0) > - > -#define REG_GPIO_PON_MODE 0x021c > -#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26) > -#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25) > -#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24) > -#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23) > -#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22) > -#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21) > -#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20) > -#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19) > -#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18) > -#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17) > -#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16) > -#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15) > -#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) > -#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) > -#define GPIO_PCIE_RESET2_MASK BIT(12) > -#define SIPO_RCLK_MODE_MASK BIT(11) > -#define GPIO_PCIE_RESET1_MASK BIT(10) > -#define GPIO_PCIE_RESET0_MASK BIT(9) > -#define GPIO_UART5_MODE_MASK BIT(8) > -#define GPIO_UART4_MODE_MASK BIT(7) > -#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) > -#define GPIO_HSUART_MODE_MASK BIT(5) > -#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) > -#define GPIO_UART2_MODE_MASK BIT(3) > -#define GPIO_SIPO_MODE_MASK BIT(2) > -#define GPIO_EMMC_MODE_MASK BIT(1) > -#define GPIO_PON_MODE_MASK BIT(0) > - > -#define REG_NPU_UART_EN 0x0224 > -#define JTAG_UDI_EN_MASK BIT(4) > -#define JTAG_DFD_EN_MASK BIT(3) > - > -#define REG_FORCE_GPIO_EN 0x0228 > -#define FORCE_GPIO_EN(n) BIT(n) > - > -/* LED MAP */ > -#define REG_LAN_LED0_MAPPING 0x027c > -#define REG_LAN_LED1_MAPPING 0x0280 > - > -#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) > -#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (= _n)) > - > -#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) > -#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (= _n)) > - > -#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) > -#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (= _n)) > - > -#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) > -#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (= _n)) > - > -#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) > -#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (= _n)) > - > -/* CONF */ > -#define REG_I2C_SDA_E2 0x001c > -#define AN7583_I2C1_SCL_E2_MASK BIT(16) > -#define AN7583_I2C1_SDA_E2_MASK BIT(15) > -#define SPI_MISO_E2_MASK BIT(14) > -#define SPI_MOSI_E2_MASK BIT(13) > -#define SPI_CLK_E2_MASK BIT(12) > -#define SPI_CS0_E2_MASK BIT(11) > -#define PCIE2_RESET_E2_MASK BIT(10) > -#define PCIE1_RESET_E2_MASK BIT(9) > -#define PCIE0_RESET_E2_MASK BIT(8) > -#define AN7583_MDIO_0_E2_MASK BIT(5) > -#define AN7583_MDC_0_E2_MASK BIT(4) > -#define UART1_RXD_E2_MASK BIT(3) > -#define UART1_TXD_E2_MASK BIT(2) > -#define I2C_SCL_E2_MASK BIT(1) > -#define I2C_SDA_E2_MASK BIT(0) > - > -#define REG_I2C_SDA_E4 0x0020 > -#define AN7583_I2C1_SCL_E4_MASK BIT(16) > -#define AN7583_I2C1_SDA_E4_MASK BIT(15) > -#define SPI_MISO_E4_MASK BIT(14) > -#define SPI_MOSI_E4_MASK BIT(13) > -#define SPI_CLK_E4_MASK BIT(12) > -#define SPI_CS0_E4_MASK BIT(11) > -#define PCIE2_RESET_E4_MASK BIT(10) > -#define PCIE1_RESET_E4_MASK BIT(9) > -#define PCIE0_RESET_E4_MASK BIT(8) > -#define AN7583_MDIO_0_E4_MASK BIT(5) > -#define AN7583_MDC_0_E4_MASK BIT(4) > -#define UART1_RXD_E4_MASK BIT(3) > -#define UART1_TXD_E4_MASK BIT(2) > -#define I2C_SCL_E4_MASK BIT(1) > -#define I2C_SDA_E4_MASK BIT(0) > - > -#define REG_GPIO_L_E2 0x0024 > -#define REG_GPIO_L_E4 0x0028 > -#define REG_GPIO_H_E2 0x002c > -#define REG_GPIO_H_E4 0x0030 > - > -#define REG_I2C_SDA_PU 0x0044 > -#define AN7583_I2C1_SCL_PU_MASK BIT(16) > -#define AN7583_I2C1_SDA_PU_MASK BIT(15) > -#define SPI_MISO_PU_MASK BIT(14) > -#define SPI_MOSI_PU_MASK BIT(13) > -#define SPI_CLK_PU_MASK BIT(12) > -#define SPI_CS0_PU_MASK BIT(11) > -#define PCIE2_RESET_PU_MASK BIT(10) > -#define PCIE1_RESET_PU_MASK BIT(9) > -#define PCIE0_RESET_PU_MASK BIT(8) > -#define AN7583_MDIO_0_PU_MASK BIT(5) > -#define AN7583_MDC_0_PU_MASK BIT(4) > -#define UART1_RXD_PU_MASK BIT(3) > -#define UART1_TXD_PU_MASK BIT(2) > -#define I2C_SCL_PU_MASK BIT(1) > -#define I2C_SDA_PU_MASK BIT(0) > - > -#define REG_I2C_SDA_PD 0x0048 > -#define AN7583_I2C1_SCL_PD_MASK BIT(16) > -#define AN7583_I2C1_SDA_PD_MASK BIT(15) > -#define SPI_MISO_PD_MASK BIT(14) > -#define SPI_MOSI_PD_MASK BIT(13) > -#define SPI_CLK_PD_MASK BIT(12) > -#define SPI_CS0_PD_MASK BIT(11) > -#define PCIE2_RESET_PD_MASK BIT(10) > -#define PCIE1_RESET_PD_MASK BIT(9) > -#define PCIE0_RESET_PD_MASK BIT(8) > -#define AN7583_MDIO_0_PD_MASK BIT(5) > -#define AN7583_MDC_0_PD_MASK BIT(4) > -#define UART1_RXD_PD_MASK BIT(3) > -#define UART1_TXD_PD_MASK BIT(2) > -#define I2C_SCL_PD_MASK BIT(1) > -#define I2C_SDA_PD_MASK BIT(0) > - > -#define REG_GPIO_L_PU 0x004c > -#define REG_GPIO_L_PD 0x0050 > -#define REG_GPIO_H_PU 0x0054 > -#define REG_GPIO_H_PD 0x0058 > - > -#define REG_PCIE_RESET_OD 0x018c > -#define PCIE2_RESET_OD_MASK BIT(2) > -#define PCIE1_RESET_OD_MASK BIT(1) > -#define PCIE0_RESET_OD_MASK BIT(0) > - > -/* GPIOs */ > -#define REG_GPIO_CTRL 0x0000 > -#define REG_GPIO_DATA 0x0004 > -#define REG_GPIO_INT 0x0008 > -#define REG_GPIO_INT_EDGE 0x000c > -#define REG_GPIO_INT_LEVEL 0x0010 > -#define REG_GPIO_OE 0x0014 > -#define REG_GPIO_CTRL1 0x0020 > -#define REG_GPIO_CTRL2 0x0060 > -#define REG_GPIO_CTRL3 0x0064 > - > -/* PWM MODE CONF */ > -#define REG_GPIO_FLASH_MODE_CFG 0x0034 > -#define GPIO15_FLASH_MODE_CFG BIT(15) > -#define GPIO14_FLASH_MODE_CFG BIT(14) > -#define GPIO13_FLASH_MODE_CFG BIT(13) > -#define GPIO12_FLASH_MODE_CFG BIT(12) > -#define GPIO11_FLASH_MODE_CFG BIT(11) > -#define GPIO10_FLASH_MODE_CFG BIT(10) > -#define GPIO9_FLASH_MODE_CFG BIT(9) > -#define GPIO8_FLASH_MODE_CFG BIT(8) > -#define GPIO7_FLASH_MODE_CFG BIT(7) > -#define GPIO6_FLASH_MODE_CFG BIT(6) > -#define GPIO5_FLASH_MODE_CFG BIT(5) > -#define GPIO4_FLASH_MODE_CFG BIT(4) > -#define GPIO3_FLASH_MODE_CFG BIT(3) > -#define GPIO2_FLASH_MODE_CFG BIT(2) > -#define GPIO1_FLASH_MODE_CFG BIT(1) > -#define GPIO0_FLASH_MODE_CFG BIT(0) > - > -/* PWM MODE CONF EXT */ > -#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 > -#define GPIO51_FLASH_MODE_CFG BIT(31) > -#define GPIO50_FLASH_MODE_CFG BIT(30) > -#define GPIO49_FLASH_MODE_CFG BIT(29) > -#define GPIO48_FLASH_MODE_CFG BIT(28) > -#define GPIO47_FLASH_MODE_CFG BIT(27) > -#define GPIO46_FLASH_MODE_CFG BIT(26) > -#define GPIO45_FLASH_MODE_CFG BIT(25) > -#define GPIO44_FLASH_MODE_CFG BIT(24) > -#define GPIO43_FLASH_MODE_CFG BIT(23) > -#define GPIO42_FLASH_MODE_CFG BIT(22) > -#define GPIO41_FLASH_MODE_CFG BIT(21) > -#define GPIO40_FLASH_MODE_CFG BIT(20) > -#define GPIO39_FLASH_MODE_CFG BIT(19) > -#define GPIO38_FLASH_MODE_CFG BIT(18) > -#define GPIO37_FLASH_MODE_CFG BIT(17) > -#define GPIO36_FLASH_MODE_CFG BIT(16) > -#define GPIO31_FLASH_MODE_CFG BIT(15) > -#define GPIO30_FLASH_MODE_CFG BIT(14) > -#define GPIO29_FLASH_MODE_CFG BIT(13) > -#define GPIO28_FLASH_MODE_CFG BIT(12) > -#define GPIO27_FLASH_MODE_CFG BIT(11) > -#define GPIO26_FLASH_MODE_CFG BIT(10) > -#define GPIO25_FLASH_MODE_CFG BIT(9) > -#define GPIO24_FLASH_MODE_CFG BIT(8) > -#define GPIO23_FLASH_MODE_CFG BIT(7) > -#define GPIO22_FLASH_MODE_CFG BIT(6) > -#define GPIO21_FLASH_MODE_CFG BIT(5) > -#define GPIO20_FLASH_MODE_CFG BIT(4) > -#define GPIO19_FLASH_MODE_CFG BIT(3) > -#define GPIO18_FLASH_MODE_CFG BIT(2) > -#define GPIO17_FLASH_MODE_CFG BIT(1) > -#define GPIO16_FLASH_MODE_CFG BIT(0) > - > -#define REG_GPIO_DATA1 0x0070 > -#define REG_GPIO_OE1 0x0078 > -#define REG_GPIO_INT1 0x007c > -#define REG_GPIO_INT_EDGE1 0x0080 > -#define REG_GPIO_INT_EDGE2 0x0084 > -#define REG_GPIO_INT_EDGE3 0x0088 > -#define REG_GPIO_INT_LEVEL1 0x008c > -#define REG_GPIO_INT_LEVEL2 0x0090 > -#define REG_GPIO_INT_LEVEL3 0x0094 > - > -#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ > - { \ > - .name =3D (gpio), \ > - .regmap[0] =3D { \ > - AIROHA_FUNC_MUX, \ > - REG_GPIO_PON_MODE, \ > - (mux_val), \ > - (mux_val) \ > - }, \ > - .regmap_size =3D 1, \ > - } > - > -#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ > - { \ > - .name =3D (gpio), \ > - .regmap[0] =3D { \ > - AIROHA_FUNC_PWM_EXT_MUX, \ > - REG_GPIO_FLASH_MODE_CFG_EXT, \ > - (mux_val), \ > - 0 \ > - }, \ > - .regmap[1] =3D { \ > - AIROHA_FUNC_MUX, \ > - REG_GPIO_PON_MODE, \ > - (smux_val), \ > - (smux_val) \ > - }, \ > - .regmap_size =3D 2, \ > - } > - > -/* PWM */ > -#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ > - { \ > - .name =3D (gpio), \ > - .regmap[0] =3D { \ > - AIROHA_FUNC_PWM_MUX, \ > - REG_GPIO_FLASH_MODE_CFG, \ > - (mux_val), \ > - (mux_val) \ > - }, \ > - .regmap_size =3D 1, \ > - } > - > -#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ > - { \ > - .name =3D (gpio), \ > - .regmap[0] =3D { \ > - AIROHA_FUNC_PWM_EXT_MUX, \ > - REG_GPIO_FLASH_MODE_CFG_EXT, \ > - (mux_val), \ > - (mux_val) \ > - }, \ > - .regmap_size =3D 1, \ > - } > - > -#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ > - { \ > - .name =3D (gpio), \ > - .regmap[0] =3D { \ > - AIROHA_FUNC_PWM_EXT_MUX, \ > - REG_GPIO_FLASH_MODE_CFG_EXT, \ > - (mux_val), \ > - (mux_val) \ > - }, \ > - .regmap[1] =3D { \ > - AIROHA_FUNC_MUX, \ > - REG_GPIO_PON_MODE, \ > - (smux_val), \ > - (smux_val) \ > - }, \ > - .regmap_size =3D 2, \ > - } > - > -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ > - { \ > - .name =3D (gpio), \ > - .regmap[0] =3D { \ > - AIROHA_FUNC_MUX, \ > - REG_GPIO_2ND_I2C_MODE, \ > - (mux_val), \ > - (mux_val), \ > - }, \ > - .regmap[1] =3D { \ > - AIROHA_FUNC_MUX, \ > - REG_LAN_LED0_MAPPING, \ > - (map_mask), \ > - (map_val), \ > - }, \ > - .regmap_size =3D 2, \ > - } > - > -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ > - { \ > - .name =3D (gpio), \ > - .regmap[0] =3D { \ > - AIROHA_FUNC_MUX, \ > - REG_GPIO_2ND_I2C_MODE, \ > - (mux_val), \ > - (mux_val), \ > - }, \ > - .regmap[1] =3D { \ > - AIROHA_FUNC_MUX, \ > - REG_LAN_LED1_MAPPING, \ > - (map_mask), \ > - (map_val), \ > - }, \ > - .regmap_size =3D 2, \ > - } > - > #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ > airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ > (pin), (val)) > @@ -433,1935 +74,6 @@ static const u32 irq_edge_regs[] =3D { > REG_GPIO_INT_EDGE3 > }; > =20 > -static struct pinctrl_pin_desc en7581_pinctrl_pins[] =3D { > - PINCTRL_PIN(0, "uart1_txd"), > - PINCTRL_PIN(1, "uart1_rxd"), > - PINCTRL_PIN(2, "i2c_scl"), > - PINCTRL_PIN(3, "i2c_sda"), > - PINCTRL_PIN(4, "spi_cs0"), > - PINCTRL_PIN(5, "spi_clk"), > - PINCTRL_PIN(6, "spi_mosi"), > - PINCTRL_PIN(7, "spi_miso"), > - PINCTRL_PIN(13, "gpio0"), > - PINCTRL_PIN(14, "gpio1"), > - PINCTRL_PIN(15, "gpio2"), > - PINCTRL_PIN(16, "gpio3"), > - PINCTRL_PIN(17, "gpio4"), > - PINCTRL_PIN(18, "gpio5"), > - PINCTRL_PIN(19, "gpio6"), > - PINCTRL_PIN(20, "gpio7"), > - PINCTRL_PIN(21, "gpio8"), > - PINCTRL_PIN(22, "gpio9"), > - PINCTRL_PIN(23, "gpio10"), > - PINCTRL_PIN(24, "gpio11"), > - PINCTRL_PIN(25, "gpio12"), > - PINCTRL_PIN(26, "gpio13"), > - PINCTRL_PIN(27, "gpio14"), > - PINCTRL_PIN(28, "gpio15"), > - PINCTRL_PIN(29, "gpio16"), > - PINCTRL_PIN(30, "gpio17"), > - PINCTRL_PIN(31, "gpio18"), > - PINCTRL_PIN(32, "gpio19"), > - PINCTRL_PIN(33, "gpio20"), > - PINCTRL_PIN(34, "gpio21"), > - PINCTRL_PIN(35, "gpio22"), > - PINCTRL_PIN(36, "gpio23"), > - PINCTRL_PIN(37, "gpio24"), > - PINCTRL_PIN(38, "gpio25"), > - PINCTRL_PIN(39, "gpio26"), > - PINCTRL_PIN(40, "gpio27"), > - PINCTRL_PIN(41, "gpio28"), > - PINCTRL_PIN(42, "gpio29"), > - PINCTRL_PIN(43, "gpio30"), > - PINCTRL_PIN(44, "gpio31"), > - PINCTRL_PIN(45, "gpio32"), > - PINCTRL_PIN(46, "gpio33"), > - PINCTRL_PIN(47, "gpio34"), > - PINCTRL_PIN(48, "gpio35"), > - PINCTRL_PIN(49, "gpio36"), > - PINCTRL_PIN(50, "gpio37"), > - PINCTRL_PIN(51, "gpio38"), > - PINCTRL_PIN(52, "gpio39"), > - PINCTRL_PIN(53, "gpio40"), > - PINCTRL_PIN(54, "gpio41"), > - PINCTRL_PIN(55, "gpio42"), > - PINCTRL_PIN(56, "gpio43"), > - PINCTRL_PIN(57, "gpio44"), > - PINCTRL_PIN(58, "gpio45"), > - PINCTRL_PIN(59, "gpio46"), > - PINCTRL_PIN(60, "pcie_reset0"), > - PINCTRL_PIN(61, "pcie_reset1"), > - PINCTRL_PIN(62, "pcie_reset2"), > -}; > - > -static const int en7581_pon_pins[] =3D { 49, 50, 51, 52, 53, 54 }; > -static const int en7581_pon_tod_1pps_pins[] =3D { 46 }; > -static const int en7581_gsw_tod_1pps_pins[] =3D { 46 }; > -static const int en7581_sipo_pins[] =3D { 16, 17 }; > -static const int en7581_sipo_rclk_pins[] =3D { 16, 17, 43 }; > -static const int en7581_mdio_pins[] =3D { 14, 15 }; > -static const int en7581_uart2_pins[] =3D { 48, 55 }; > -static const int en7581_uart2_cts_rts_pins[] =3D { 46, 47 }; > -static const int en7581_hsuart_pins[] =3D { 28, 29 }; > -static const int en7581_hsuart_cts_rts_pins[] =3D { 26, 27 }; > -static const int en7581_uart4_pins[] =3D { 38, 39 }; > -static const int en7581_uart5_pins[] =3D { 18, 19 }; > -static const int en7581_i2c0_pins[] =3D { 2, 3 }; > -static const int en7581_i2c1_pins[] =3D { 14, 15 }; > -static const int en7581_jtag_udi_pins[] =3D { 16, 17, 18, 19, 20 }; > -static const int en7581_jtag_dfd_pins[] =3D { 16, 17, 18, 19, 20 }; > -static const int en7581_i2s_pins[] =3D { 26, 27, 28, 29 }; > -static const int en7581_pcm1_pins[] =3D { 22, 23, 24, 25 }; > -static const int en7581_pcm2_pins[] =3D { 18, 19, 20, 21 }; > -static const int en7581_spi_quad_pins[] =3D { 32, 33 }; > -static const int en7581_spi_pins[] =3D { 4, 5, 6, 7 }; > -static const int en7581_spi_cs1_pins[] =3D { 34 }; > -static const int en7581_pcm_spi_pins[] =3D { 18, 19, 20, 21, 22, 23, 24,= 25 }; > -static const int en7581_pcm_spi_int_pins[] =3D { 14 }; > -static const int en7581_pcm_spi_rst_pins[] =3D { 15 }; > -static const int en7581_pcm_spi_cs1_pins[] =3D { 43 }; > -static const int en7581_pcm_spi_cs2_pins[] =3D { 40 }; > -static const int en7581_pcm_spi_cs2_p128_pins[] =3D { 40 }; > -static const int en7581_pcm_spi_cs2_p156_pins[] =3D { 40 }; > -static const int en7581_pcm_spi_cs3_pins[] =3D { 41 }; > -static const int en7581_pcm_spi_cs4_pins[] =3D { 42 }; > -static const int en7581_emmc_pins[] =3D { 4, 5, 6, 30, 31, 32, 33, 34, 3= 5, 36, 37 }; > -static const int en7581_pnand_pins[] =3D { 4, 5, 6, 7, 30, 31, 32, 33, 3= 4, 35, 36, 37, 38, 39, 40, 41, 42 }; > -static const int en7581_gpio0_pins[] =3D { 13 }; > -static const int en7581_gpio1_pins[] =3D { 14 }; > -static const int en7581_gpio2_pins[] =3D { 15 }; > -static const int en7581_gpio3_pins[] =3D { 16 }; > -static const int en7581_gpio4_pins[] =3D { 17 }; > -static const int en7581_gpio5_pins[] =3D { 18 }; > -static const int en7581_gpio6_pins[] =3D { 19 }; > -static const int en7581_gpio7_pins[] =3D { 20 }; > -static const int en7581_gpio8_pins[] =3D { 21 }; > -static const int en7581_gpio9_pins[] =3D { 22 }; > -static const int en7581_gpio10_pins[] =3D { 23 }; > -static const int en7581_gpio11_pins[] =3D { 24 }; > -static const int en7581_gpio12_pins[] =3D { 25 }; > -static const int en7581_gpio13_pins[] =3D { 26 }; > -static const int en7581_gpio14_pins[] =3D { 27 }; > -static const int en7581_gpio15_pins[] =3D { 28 }; > -static const int en7581_gpio16_pins[] =3D { 29 }; > -static const int en7581_gpio17_pins[] =3D { 30 }; > -static const int en7581_gpio18_pins[] =3D { 31 }; > -static const int en7581_gpio19_pins[] =3D { 32 }; > -static const int en7581_gpio20_pins[] =3D { 33 }; > -static const int en7581_gpio21_pins[] =3D { 34 }; > -static const int en7581_gpio22_pins[] =3D { 35 }; > -static const int en7581_gpio23_pins[] =3D { 36 }; > -static const int en7581_gpio24_pins[] =3D { 37 }; > -static const int en7581_gpio25_pins[] =3D { 38 }; > -static const int en7581_gpio26_pins[] =3D { 39 }; > -static const int en7581_gpio27_pins[] =3D { 40 }; > -static const int en7581_gpio28_pins[] =3D { 41 }; > -static const int en7581_gpio29_pins[] =3D { 42 }; > -static const int en7581_gpio30_pins[] =3D { 43 }; > -static const int en7581_gpio31_pins[] =3D { 44 }; > -static const int en7581_gpio32_pins[] =3D { 45 }; > -static const int en7581_gpio33_pins[] =3D { 46 }; > -static const int en7581_gpio34_pins[] =3D { 47 }; > -static const int en7581_gpio35_pins[] =3D { 48 }; > -static const int en7581_gpio36_pins[] =3D { 49 }; > -static const int en7581_gpio37_pins[] =3D { 50 }; > -static const int en7581_gpio38_pins[] =3D { 51 }; > -static const int en7581_gpio39_pins[] =3D { 52 }; > -static const int en7581_gpio40_pins[] =3D { 53 }; > -static const int en7581_gpio41_pins[] =3D { 54 }; > -static const int en7581_gpio42_pins[] =3D { 55 }; > -static const int en7581_gpio43_pins[] =3D { 56 }; > -static const int en7581_gpio44_pins[] =3D { 57 }; > -static const int en7581_gpio45_pins[] =3D { 58 }; > -static const int en7581_gpio46_pins[] =3D { 59 }; > -static const int en7581_gpio47_pins[] =3D { 60 }; > -static const int en7581_gpio48_pins[] =3D { 61 }; > -static const int en7581_gpio49_pins[] =3D { 62 }; > -static const int en7581_pcie_reset0_pins[] =3D { 60 }; > -static const int en7581_pcie_reset1_pins[] =3D { 61 }; > -static const int en7581_pcie_reset2_pins[] =3D { 62 }; > - > -static const struct pingroup en7581_pinctrl_groups[] =3D { > - PINCTRL_PIN_GROUP("pon", en7581_pon), > - PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), > - PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), > - PINCTRL_PIN_GROUP("sipo", en7581_sipo), > - PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), > - PINCTRL_PIN_GROUP("mdio", en7581_mdio), > - PINCTRL_PIN_GROUP("uart2", en7581_uart2), > - PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), > - PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), > - PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), > - PINCTRL_PIN_GROUP("uart4", en7581_uart4), > - PINCTRL_PIN_GROUP("uart5", en7581_uart5), > - PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), > - PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), > - PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), > - PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), > - PINCTRL_PIN_GROUP("i2s", en7581_i2s), > - PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), > - PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), > - PINCTRL_PIN_GROUP("spi", en7581_spi), > - PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), > - PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), > - PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), > - PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), > - PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), > - PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), > - PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), > - PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), > - PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), > - PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), > - PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), > - PINCTRL_PIN_GROUP("emmc", en7581_emmc), > - PINCTRL_PIN_GROUP("pnand", en7581_pnand), > - PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), > - PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), > - PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), > - PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), > - PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), > - PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), > - PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), > - PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), > - PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), > - PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), > - PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), > - PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), > - PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), > - PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), > - PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), > - PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), > - PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), > - PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), > - PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), > - PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), > - PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), > - PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), > - PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), > - PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), > - PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), > - PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), > - PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), > - PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), > - PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), > - PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), > - PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), > - PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), > - PINCTRL_PIN_GROUP("gpio32", en7581_gpio32), > - PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), > - PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), > - PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), > - PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), > - PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), > - PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), > - PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), > - PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), > - PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), > - PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), > - PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), > - PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), > - PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), > - PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), > - PINCTRL_PIN_GROUP("gpio47", en7581_gpio47), > - PINCTRL_PIN_GROUP("gpio48", en7581_gpio48), > - PINCTRL_PIN_GROUP("gpio49", en7581_gpio49), > - PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), > - PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), > - PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), > -}; > - > -static struct pinctrl_pin_desc an7583_pinctrl_pins[] =3D { > - PINCTRL_PIN(2, "gpio0"), > - PINCTRL_PIN(3, "gpio1"), > - PINCTRL_PIN(4, "gpio2"), > - PINCTRL_PIN(5, "gpio3"), > - PINCTRL_PIN(6, "gpio4"), > - PINCTRL_PIN(7, "gpio5"), > - PINCTRL_PIN(8, "gpio6"), > - PINCTRL_PIN(9, "gpio7"), > - PINCTRL_PIN(10, "gpio8"), > - PINCTRL_PIN(11, "gpio9"), > - PINCTRL_PIN(12, "gpio10"), > - PINCTRL_PIN(13, "gpio11"), > - PINCTRL_PIN(14, "gpio12"), > - PINCTRL_PIN(15, "gpio13"), > - PINCTRL_PIN(16, "gpio14"), > - PINCTRL_PIN(17, "gpio15"), > - PINCTRL_PIN(18, "gpio16"), > - PINCTRL_PIN(19, "gpio17"), > - PINCTRL_PIN(20, "gpio18"), > - PINCTRL_PIN(21, "gpio19"), > - PINCTRL_PIN(22, "gpio20"), > - PINCTRL_PIN(23, "gpio21"), > - PINCTRL_PIN(24, "gpio22"), > - PINCTRL_PIN(25, "gpio23"), > - PINCTRL_PIN(26, "gpio24"), > - PINCTRL_PIN(27, "gpio25"), > - PINCTRL_PIN(28, "gpio26"), > - PINCTRL_PIN(29, "gpio27"), > - PINCTRL_PIN(30, "gpio28"), > - PINCTRL_PIN(31, "gpio29"), > - PINCTRL_PIN(32, "gpio30"), > - PINCTRL_PIN(33, "gpio31"), > - PINCTRL_PIN(34, "gpio32"), > - PINCTRL_PIN(35, "gpio33"), > - PINCTRL_PIN(36, "gpio34"), > - PINCTRL_PIN(37, "gpio35"), > - PINCTRL_PIN(38, "gpio36"), > - PINCTRL_PIN(39, "gpio37"), > - PINCTRL_PIN(40, "gpio38"), > - PINCTRL_PIN(41, "i2c0_scl"), > - PINCTRL_PIN(42, "i2c0_sda"), > - PINCTRL_PIN(43, "i2c1_scl"), > - PINCTRL_PIN(44, "i2c1_sda"), > - PINCTRL_PIN(45, "spi_clk"), > - PINCTRL_PIN(46, "spi_cs"), > - PINCTRL_PIN(47, "spi_mosi"), > - PINCTRL_PIN(48, "spi_miso"), > - PINCTRL_PIN(49, "uart_txd"), > - PINCTRL_PIN(50, "uart_rxd"), > - PINCTRL_PIN(51, "pcie_reset0"), > - PINCTRL_PIN(52, "pcie_reset1"), > - PINCTRL_PIN(53, "mdc_0"), > - PINCTRL_PIN(54, "mdio_0"), > -}; > - > -static const int an7583_pon_pins[] =3D { 15, 16, 17, 18, 19, 20 }; > -static const int an7583_pon_tod_1pps_pins[] =3D { 32 }; > -static const int an7583_gsw_tod_1pps_pins[] =3D { 32 }; > -static const int an7583_sipo_pins[] =3D { 34, 35 }; > -static const int an7583_sipo_rclk_pins[] =3D { 34, 35, 33 }; > -static const int an7583_mdio_pins[] =3D { 43, 44 }; > -static const int an7583_uart2_pins[] =3D { 34, 35 }; > -static const int an7583_uart2_cts_rts_pins[] =3D { 32, 33 }; > -static const int an7583_hsuart_pins[] =3D { 30, 31 }; > -static const int an7583_hsuart_cts_rts_pins[] =3D { 28, 29 }; > -static const int an7583_npu_uart_pins[] =3D { 7, 8 }; > -static const int an7583_uart4_pins[] =3D { 7, 8 }; > -static const int an7583_uart5_pins[] =3D { 23, 24 }; > -static const int an7583_i2c0_pins[] =3D { 41, 42 }; > -static const int an7583_i2c1_pins[] =3D { 43, 44 }; > -static const int an7583_jtag_udi_pins[] =3D { 23, 24, 22, 25, 26 }; > -static const int an7583_jtag_dfd_pins[] =3D { 23, 24, 22, 25, 26 }; > -static const int an7583_pcm1_pins[] =3D { 10, 11, 12, 13, 14 }; > -static const int an7583_pcm2_pins[] =3D { 28, 29, 30, 31, 24 }; > -static const int an7583_spi_pins[] =3D { 28, 29, 30, 31 }; > -static const int an7583_spi_quad_pins[] =3D { 25, 26 }; > -static const int an7583_spi_cs1_pins[] =3D { 27 }; > -static const int an7583_pcm_spi_pins[] =3D { 28, 29, 30, 31, 10, 11, 12,= 13 }; > -static const int an7583_pcm_spi_rst_pins[] =3D { 14 }; > -static const int an7583_pcm_spi_cs1_pins[] =3D { 24 }; > -static const int an7583_emmc_pins[] =3D { 7, 8, 9, 22, 23, 24, 25, 26, 4= 5, 46, 47 }; > -static const int an7583_pnand_pins[] =3D { 7, 8, 9, 22, 23, 24, 25, 26, = 27, 28, 29, 30, 31, 45, 46, 47, 48 }; > -static const int an7583_gpio0_pins[] =3D { 2 }; > -static const int an7583_gpio1_pins[] =3D { 3 }; > -static const int an7583_gpio2_pins[] =3D { 4 }; > -static const int an7583_gpio3_pins[] =3D { 5 }; > -static const int an7583_gpio4_pins[] =3D { 6 }; > -static const int an7583_gpio5_pins[] =3D { 7 }; > -static const int an7583_gpio6_pins[] =3D { 8 }; > -static const int an7583_gpio7_pins[] =3D { 9 }; > -static const int an7583_gpio8_pins[] =3D { 10 }; > -static const int an7583_gpio9_pins[] =3D { 11 }; > -static const int an7583_gpio10_pins[] =3D { 12 }; > -static const int an7583_gpio11_pins[] =3D { 13 }; > -static const int an7583_gpio12_pins[] =3D { 14 }; > -static const int an7583_gpio13_pins[] =3D { 15 }; > -static const int an7583_gpio14_pins[] =3D { 16 }; > -static const int an7583_gpio15_pins[] =3D { 17 }; > -static const int an7583_gpio16_pins[] =3D { 18 }; > -static const int an7583_gpio17_pins[] =3D { 19 }; > -static const int an7583_gpio18_pins[] =3D { 20 }; > -static const int an7583_gpio19_pins[] =3D { 21 }; > -static const int an7583_gpio20_pins[] =3D { 22 }; > -static const int an7583_gpio21_pins[] =3D { 23 }; > -static const int an7583_gpio22_pins[] =3D { 24 }; > -static const int an7583_gpio23_pins[] =3D { 25 }; > -static const int an7583_gpio24_pins[] =3D { 26 }; > -static const int an7583_gpio25_pins[] =3D { 27 }; > -static const int an7583_gpio26_pins[] =3D { 28 }; > -static const int an7583_gpio27_pins[] =3D { 29 }; > -static const int an7583_gpio28_pins[] =3D { 30 }; > -static const int an7583_gpio29_pins[] =3D { 31 }; > -static const int an7583_gpio30_pins[] =3D { 32 }; > -static const int an7583_gpio31_pins[] =3D { 33 }; > -static const int an7583_gpio32_pins[] =3D { 34 }; > -static const int an7583_gpio33_pins[] =3D { 35 }; > -static const int an7583_gpio34_pins[] =3D { 36 }; > -static const int an7583_gpio35_pins[] =3D { 37 }; > -static const int an7583_gpio36_pins[] =3D { 38 }; > -static const int an7583_gpio37_pins[] =3D { 39 }; > -static const int an7583_gpio38_pins[] =3D { 40 }; > -static const int an7583_gpio39_pins[] =3D { 41 }; > -static const int an7583_gpio40_pins[] =3D { 42 }; > -static const int an7583_gpio41_pins[] =3D { 43 }; > -static const int an7583_gpio42_pins[] =3D { 44 }; > -static const int an7583_gpio43_pins[] =3D { 45 }; > -static const int an7583_gpio44_pins[] =3D { 46 }; > -static const int an7583_gpio45_pins[] =3D { 47 }; > -static const int an7583_gpio46_pins[] =3D { 48 }; > -static const int an7583_gpio47_pins[] =3D { 49 }; > -static const int an7583_gpio48_pins[] =3D { 50 }; > -static const int an7583_gpio49_pins[] =3D { 51 }; > -static const int an7583_gpio50_pins[] =3D { 52 }; > -static const int an7583_gpio51_pins[] =3D { 53 }; > -static const int an7583_gpio52_pins[] =3D { 54 }; > -static const int an7583_pcie_reset0_pins[] =3D { 51 }; > -static const int an7583_pcie_reset1_pins[] =3D { 52 }; > - > -static const struct pingroup an7583_pinctrl_groups[] =3D { > - PINCTRL_PIN_GROUP("pon", an7583_pon), > - PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), > - PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), > - PINCTRL_PIN_GROUP("sipo", an7583_sipo), > - PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), > - PINCTRL_PIN_GROUP("mdio", an7583_mdio), > - PINCTRL_PIN_GROUP("uart2", an7583_uart2), > - PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), > - PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), > - PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), > - PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), > - PINCTRL_PIN_GROUP("uart4", an7583_uart4), > - PINCTRL_PIN_GROUP("uart5", an7583_uart5), > - PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), > - PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), > - PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), > - PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), > - PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), > - PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), > - PINCTRL_PIN_GROUP("spi", an7583_spi), > - PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), > - PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), > - PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), > - PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), > - PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), > - PINCTRL_PIN_GROUP("emmc", an7583_emmc), > - PINCTRL_PIN_GROUP("pnand", an7583_pnand), > - PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), > - PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), > - PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), > - PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), > - PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), > - PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), > - PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), > - PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), > - PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), > - PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), > - PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), > - PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), > - PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), > - PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), > - PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), > - PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), > - PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), > - PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), > - PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), > - PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), > - PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), > - PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), > - PINCTRL_PIN_GROUP("gpio22", an7583_gpio22), > - PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), > - PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), > - PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), > - PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), > - PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), > - PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), > - PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), > - PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), > - PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), > - PINCTRL_PIN_GROUP("gpio32", an7583_gpio32), > - PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), > - PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), > - PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), > - PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), > - PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), > - PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), > - PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), > - PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), > - PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), > - PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), > - PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), > - PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), > - PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), > - PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), > - PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), > - PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), > - PINCTRL_PIN_GROUP("gpio49", an7583_gpio49), > - PINCTRL_PIN_GROUP("gpio50", an7583_gpio50), > - PINCTRL_PIN_GROUP("gpio51", an7583_gpio51), > - PINCTRL_PIN_GROUP("gpio52", an7583_gpio52), > - PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), > - PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), > -}; > - > -static const char *const pon_groups[] =3D { "pon" }; > -static const char *const tod_1pps_groups[] =3D { "pon_tod_1pps", "gsw_to= d_1pps" }; > -static const char *const sipo_groups[] =3D { "sipo", "sipo_rclk" }; > -static const char *const mdio_groups[] =3D { "mdio" }; > -static const char *const an7583_mdio_groups[] =3D { "mdio" }; > -static const char *const uart_groups[] =3D { "uart2", "uart2_cts_rts", "= hsuart", > - "hsuart_cts_rts", "uart4", > - "uart5" }; > -static const char *const i2c_groups[] =3D { "i2c1" }; > -static const char *const jtag_groups[] =3D { "jtag_udi", "jtag_dfd" }; > -static const char *const pcm_groups[] =3D { "pcm1", "pcm2" }; > -static const char *const spi_groups[] =3D { "spi_quad", "spi_cs1" }; > -static const char *const pcm_spi_groups[] =3D { "pcm_spi", "pcm_spi_int", > - "pcm_spi_rst", "pcm_spi_cs1", > - "pcm_spi_cs2_p156", > - "pcm_spi_cs2_p128", > - "pcm_spi_cs3", "pcm_spi_cs4" }; > -static const char *const an7583_pcm_spi_groups[] =3D { "pcm_spi", > - "pcm_spi_rst", "pcm_spi_cs1" }; > -static const char *const i2s_groups[] =3D { "i2s" }; > -static const char *const emmc_groups[] =3D { "emmc" }; > -static const char *const pnand_groups[] =3D { "pnand" }; > -static const char *const gpio_groups[] =3D { "gpio47", "gpio48", "gpio49= " }; > -static const char *const pcie_reset_groups[] =3D { "pcie_reset0", "pcie_= reset1", > - "pcie_reset2" }; > -static const char *const an7583_gpio_groups[] =3D { "gpio39", "gpio40", = "gpio41", > - "gpio42", "gpio43", "gpio44", > - "gpio45", "gpio46", "gpio47", > - "gpio48", "gpio49", "gpio50", > - "gpio51", "gpio52" }; > -static const char *const an7583_pcie_reset_groups[] =3D { "pcie_reset0",= "pcie_reset1" }; > -static const char *const pwm_groups[] =3D { "gpio0", "gpio1", > - "gpio2", "gpio3", > - "gpio4", "gpio5", > - "gpio6", "gpio7", > - "gpio8", "gpio9", > - "gpio10", "gpio11", > - "gpio12", "gpio13", > - "gpio14", "gpio15", > - "gpio16", "gpio17", > - "gpio18", "gpio19", > - "gpio20", "gpio21", > - "gpio22", "gpio23", > - "gpio24", "gpio25", > - "gpio26", "gpio27", > - "gpio28", "gpio29", > - "gpio30", "gpio31", > - "gpio36", "gpio37", > - "gpio38", "gpio39", > - "gpio40", "gpio41", > - "gpio42", "gpio43", > - "gpio44", "gpio45", > - "gpio46", "gpio47", > - "gpio48", "gpio49" }; > -static const char *const an7583_pwm_groups[] =3D { "gpio0", "gpio1", > - "gpio2", "gpio3", > - "gpio4", "gpio5", > - "gpio6", "gpio7", > - "gpio8", "gpio9", > - "gpio10", "gpio11", > - "gpio12", "gpio13", > - "gpio14", "gpio15", > - "gpio16", "gpio17", > - "gpio18", "gpio19", > - "gpio20", "gpio21", > - "gpio22", "gpio23", > - "gpio24", "gpio25", > - "gpio26", "gpio27", > - "gpio28", "gpio29", > - "gpio30", "gpio31", > - "gpio36", "gpio37", > - "gpio38", "gpio39", > - "gpio40", "gpio41", > - "gpio42", "gpio43", > - "gpio44", "gpio45", > - "gpio46", "gpio47", > - "gpio48", "gpio49", > - "gpio50", "gpio51" }; > -static const char *const phy1_led0_groups[] =3D { "gpio33", "gpio34", > - "gpio35", "gpio42" }; > -static const char *const phy2_led0_groups[] =3D { "gpio33", "gpio34", > - "gpio35", "gpio42" }; > -static const char *const phy3_led0_groups[] =3D { "gpio33", "gpio34", > - "gpio35", "gpio42" }; > -static const char *const phy4_led0_groups[] =3D { "gpio33", "gpio34", > - "gpio35", "gpio42" }; > -static const char *const phy1_led1_groups[] =3D { "gpio43", "gpio44", > - "gpio45", "gpio46" }; > -static const char *const phy2_led1_groups[] =3D { "gpio43", "gpio44", > - "gpio45", "gpio46" }; > -static const char *const phy3_led1_groups[] =3D { "gpio43", "gpio44", > - "gpio45", "gpio46" }; > -static const char *const phy4_led1_groups[] =3D { "gpio43", "gpio44", > - "gpio45", "gpio46" }; > -static const char *const an7583_phy1_led0_groups[] =3D { "gpio1", "gpio2= ", > - "gpio3", "gpio4" }; > -static const char *const an7583_phy2_led0_groups[] =3D { "gpio1", "gpio2= ", > - "gpio3", "gpio4" }; > -static const char *const an7583_phy3_led0_groups[] =3D { "gpio1", "gpio2= ", > - "gpio3", "gpio4" }; > -static const char *const an7583_phy4_led0_groups[] =3D { "gpio1", "gpio2= ", > - "gpio3", "gpio4" }; > -static const char *const an7583_phy1_led1_groups[] =3D { "gpio8", "gpio9= ", > - "gpio10", "gpio11" }; > -static const char *const an7583_phy2_led1_groups[] =3D { "gpio8", "gpio9= ", > - "gpio10", "gpio11" }; > -static const char *const an7583_phy3_led1_groups[] =3D { "gpio8", "gpio9= ", > - "gpio10", "gpio11" }; > -static const char *const an7583_phy4_led1_groups[] =3D { "gpio8", "gpio9= ", > - "gpio10", "gpio11" }; > - > -static const struct airoha_pinctrl_func_group pon_func_group[] =3D { > - { > - .name =3D "pon", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_PON_MODE_MASK, > - GPIO_PON_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group tod_1pps_func_group[] =3D { > - { > - .name =3D "pon_tod_1pps", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_2ND_I2C_MODE, > - PON_TOD_1PPS_MODE_MASK, > - PON_TOD_1PPS_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "gsw_tod_1pps", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_2ND_I2C_MODE, > - GSW_TOD_1PPS_MODE_MASK, > - GSW_TOD_1PPS_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group sipo_func_group[] =3D { > - { > - .name =3D "sipo", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, > - GPIO_SIPO_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "sipo_rclk", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, > - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group mdio_func_group[] =3D { > - { > - .name =3D "mdio", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_2ND_I2C_MODE, > - GPIO_MDC_IO_MASTER_MODE_MASK, > - GPIO_MDC_IO_MASTER_MODE_MASK > - }, > - .regmap[1] =3D { > - AIROHA_FUNC_MUX, > - REG_FORCE_GPIO_EN, > - FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), > - FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) > - }, > - .regmap_size =3D 2, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = =3D { > - { > - .name =3D "mdio", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_SGMII_MDIO_MODE_MASK, > - GPIO_SGMII_MDIO_MODE_MASK > - }, > - .regmap[1] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_MDC_IO_MASTER_MODE_MASK, > - GPIO_MDC_IO_MASTER_MODE_MASK > - }, > - .regmap_size =3D 2, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group uart_func_group[] =3D { > - { > - .name =3D "uart2", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_UART2_MODE_MASK, > - GPIO_UART2_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "uart2_cts_rts", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, > - GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "hsuart", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, > - GPIO_HSUART_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > - { > - .name =3D "hsuart_cts_rts", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, > - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "uart4", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_UART4_MODE_MASK, > - GPIO_UART4_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "uart5", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_UART5_MODE_MASK, > - GPIO_UART5_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group i2c_func_group[] =3D { > - { > - .name =3D "i2c1", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_2ND_I2C_MODE, > - GPIO_2ND_I2C_MODE_MASK, > - GPIO_2ND_I2C_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group jtag_func_group[] =3D { > - { > - .name =3D "jtag_udi", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_NPU_UART_EN, > - JTAG_UDI_EN_MASK, > - JTAG_UDI_EN_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "jtag_dfd", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_NPU_UART_EN, > - JTAG_DFD_EN_MASK, > - JTAG_DFD_EN_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group pcm_func_group[] =3D { > - { > - .name =3D "pcm1", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM1_MODE_MASK, > - GPIO_PCM1_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm2", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM2_MODE_MASK, > - GPIO_PCM2_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group spi_func_group[] =3D { > - { > - .name =3D "spi_quad", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_SPI_QUAD_MODE_MASK, > - GPIO_SPI_QUAD_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "spi_cs1", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_SPI_CS1_MODE_MASK, > - GPIO_SPI_CS1_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "spi_cs2", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_SPI_CS2_MODE_MASK, > - GPIO_SPI_CS2_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "spi_cs3", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_SPI_CS3_MODE_MASK, > - GPIO_SPI_CS3_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "spi_cs4", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_SPI_CS4_MODE_MASK, > - GPIO_SPI_CS4_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group pcm_spi_func_group[] =3D { > - { > - .name =3D "pcm_spi", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_SPI_MODE_MASK, > - GPIO_PCM_SPI_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_int", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_INT_MODE_MASK, > - GPIO_PCM_INT_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_rst", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_RESET_MODE_MASK, > - GPIO_PCM_RESET_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_cs1", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_SPI_CS1_MODE_MASK, > - GPIO_PCM_SPI_CS1_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_cs2_p128", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_SPI_CS2_MODE_P128_MASK, > - GPIO_PCM_SPI_CS2_MODE_P128_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_cs2_p156", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_SPI_CS2_MODE_P156_MASK, > - GPIO_PCM_SPI_CS2_MODE_P156_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_cs3", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_SPI_CS3_MODE_MASK, > - GPIO_PCM_SPI_CS3_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_cs4", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_SPI_CS4_MODE_MASK, > - GPIO_PCM_SPI_CS4_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[= ] =3D { > - { > - .name =3D "pcm_spi", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_SPI_MODE_MASK, > - GPIO_PCM_SPI_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_int", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_INT_MODE_MASK, > - GPIO_PCM_INT_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_rst", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_RESET_MODE_MASK, > - GPIO_PCM_RESET_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_cs1", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_SPI_CS1_MODE_MASK, > - GPIO_PCM_SPI_CS1_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_cs2", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, > - AN7583_GPIO_PCM_SPI_CS2_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_cs3", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_SPI_CS3_MODE_MASK, > - GPIO_PCM_SPI_CS3_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcm_spi_cs4", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_SPI_CS1_MODE, > - GPIO_PCM_SPI_CS4_MODE_MASK, > - GPIO_PCM_SPI_CS4_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group i2s_func_group[] =3D { > - { > - .name =3D "i2s", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_2ND_I2C_MODE, > - GPIO_I2S_MODE_MASK, > - GPIO_I2S_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group emmc_func_group[] =3D { > - { > - .name =3D "emmc", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_EMMC_MODE_MASK, > - GPIO_EMMC_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group pnand_func_group[] =3D { > - { > - .name =3D "pnand", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_PARALLEL_NAND_MODE_MASK, > - GPIO_PARALLEL_NAND_MODE_MASK > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group gpio_func_group[] =3D { > - AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, > - GPIO_PCIE_RESET0_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, > - GPIO_PCIE_RESET1_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, > - GPIO_PCIE_RESET2_MASK), > -}; > - > -static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = =3D { > - { > - .name =3D "pcie_reset0", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_PCIE_RESET0_MASK, > - 0 > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcie_reset1", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_PCIE_RESET1_MASK, > - 0 > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcie_reset2", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_PCIE_RESET2_MASK, > - 0 > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = =3D { > - AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG, > - AN7583_I2C0_SCL_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG, > - AN7583_I2C0_SDA_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG, > - AN7583_I2C1_SCL_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG, > - AN7583_I2C1_SDA_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG, > - AN7583_SPI_CLK_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG, > - AN7583_SPI_CS_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG, > - AN7583_SPI_MOSI_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG, > - AN7583_SPI_MISO_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, > - AN7583_UART_TXD_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, > - AN7583_UART_RXD_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, > - GPIO_PCIE_RESET0_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG, > - GPIO_PCIE_RESET1_MASK), > - AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG, > - AN7583_MDC_0_GPIO_MODE_MASK), > - AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK), > -}; > - > -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_gro= up[] =3D { > - { > - .name =3D "pcie_reset0", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_PCIE_RESET0_MASK, > - 0 > - }, > - .regmap_size =3D 1, > - }, { > - .name =3D "pcie_reset1", > - .regmap[0] =3D { > - AIROHA_FUNC_MUX, > - REG_GPIO_PON_MODE, > - GPIO_PCIE_RESET1_MASK, > - 0 > - }, > - .regmap_size =3D 1, > - }, > -}; > - > -static const struct airoha_pinctrl_func_group pwm_func_group[] =3D { > - AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, > - GPIO_PCIE_RESET0_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, > - GPIO_PCIE_RESET1_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, > - GPIO_PCIE_RESET2_MASK), > -}; > - > -static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = =3D { > - AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG, > - AN7583_I2C0_SCL_GPIO_MODE_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG, > - AN7583_I2C0_SDA_GPIO_MODE_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG, > - AN7583_I2C1_SCL_GPIO_MODE_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG, > - AN7583_I2C1_SDA_GPIO_MODE_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG, > - AN7583_SPI_CLK_GPIO_MODE_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG, > - AN7583_SPI_CS_GPIO_MODE_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG, > - AN7583_SPI_MOSI_GPIO_MODE_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG, > - AN7583_SPI_MISO_GPIO_MODE_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, > - AN7583_UART_TXD_GPIO_MODE_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, > - AN7583_UART_RXD_GPIO_MODE_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, > - GPIO_PCIE_RESET0_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG, > - GPIO_PCIE_RESET1_MASK), > - AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG, > - AN7583_MDC_0_GPIO_MODE_MASK), > -}; > - > -static const struct airoha_pinctrl_func_group phy1_led0_func_group[] =3D= { > - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), > -}; > - > -static const struct airoha_pinctrl_func_group phy2_led0_func_group[] =3D= { > - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), > -}; > - > -static const struct airoha_pinctrl_func_group phy3_led0_func_group[] =3D= { > - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), > -}; > - > -static const struct airoha_pinctrl_func_group phy4_led0_func_group[] =3D= { > - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), > -}; > - > -static const struct airoha_pinctrl_func_group phy1_led1_func_group[] =3D= { > - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), > -}; > - > -static const struct airoha_pinctrl_func_group phy2_led1_func_group[] =3D= { > - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), > -}; > - > -static const struct airoha_pinctrl_func_group phy3_led1_func_group[] =3D= { > - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), > -}; > - > -static const struct airoha_pinctrl_func_group phy4_led1_func_group[] =3D= { > - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), > -}; > - > -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_grou= p[] =3D { > - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), > -}; > - > -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_grou= p[] =3D { > - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), > -}; > - > -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_grou= p[] =3D { > - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), > -}; > - > -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_grou= p[] =3D { > - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), > -}; > - > -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_grou= p[] =3D { > - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), > - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), > -}; > - > -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_grou= p[] =3D { > - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), > - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), > -}; > - > -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_grou= p[] =3D { > - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), > - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), > -}; > - > -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_grou= p[] =3D { > - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, > - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, > - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, > - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), > - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, > - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), > -}; > - > -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] =3D { > - PINCTRL_FUNC_DESC("pon", pon), > - PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), > - PINCTRL_FUNC_DESC("sipo", sipo), > - PINCTRL_FUNC_DESC("mdio", mdio), > - PINCTRL_FUNC_DESC("uart", uart), > - PINCTRL_FUNC_DESC("i2c", i2c), > - PINCTRL_FUNC_DESC("jtag", jtag), > - PINCTRL_FUNC_DESC("pcm", pcm), > - PINCTRL_FUNC_DESC("spi", spi), > - PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), > - PINCTRL_FUNC_DESC("i2s", i2s), > - PINCTRL_FUNC_DESC("emmc", emmc), > - PINCTRL_FUNC_DESC("pnand", pnand), > - PINCTRL_FUNC_DESC("gpio", gpio), > - PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), > - PINCTRL_FUNC_DESC("pwm", pwm), > - PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), > - PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), > - PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), > - PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), > - PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), > - PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), > - PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), > - PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), > -}; > - > -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] =3D { > - PINCTRL_FUNC_DESC("pon", pon), > - PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), > - PINCTRL_FUNC_DESC("sipo", sipo), > - PINCTRL_FUNC_DESC("mdio", an7583_mdio), > - PINCTRL_FUNC_DESC("uart", uart), > - PINCTRL_FUNC_DESC("jtag", jtag), > - PINCTRL_FUNC_DESC("pcm", pcm), > - PINCTRL_FUNC_DESC("spi", spi), > - PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), > - PINCTRL_FUNC_DESC("emmc", emmc), > - PINCTRL_FUNC_DESC("pnand", pnand), > - PINCTRL_FUNC_DESC("gpio", an7583_gpio), > - PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), > - PINCTRL_FUNC_DESC("pwm", an7583_pwm), > - PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), > - PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), > - PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), > - PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), > - PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), > - PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), > - PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), > - PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), > -}; > - > -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] =3D= { > - PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), > - PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), > - PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), > - PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), > - PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), > - PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), > - PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), > - PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), > - PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), > - PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), > - PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), > - PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), > - PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), > - PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), > - PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), > - PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), > - PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), > - PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), > - PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), > - PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), > - PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), > - PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), > - PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), > - PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), > - PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), > - PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), > - PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), > - PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)), > - PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), > - PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), > - PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), > - PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), > - PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), > - PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), > - PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), > - PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), > - PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), > - PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), > - PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), > - PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), > - PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), > - PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), > - PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), > - PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), > - PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), > - PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), > - PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), > - PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), > - PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), > - PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), > - PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), > - PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), > - PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), > - PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), > - PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), > - PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), > - PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), > - PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), > -}; > - > -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] =3D= { > - PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), > - PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), > - PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), > - PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), > - PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), > - PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), > - PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), > - PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), > - PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), > - PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), > - PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), > - PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), > - PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), > - PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), > - PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), > - PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), > - PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), > - PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), > - PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), > - PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)), > - PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), > - PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), > - PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), > - PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), > - PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), > - PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), > - PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), > - PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), > - PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), > - PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), > - PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), > - PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), > - PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), > - PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), > - PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), > - PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), > - PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), > - PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), > - PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), > - PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), > - PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), > - PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK), > - PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK), > - PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), > - PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), > - PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), > - PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), > - PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), > - PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), > - PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), > - PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), > - PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK), > - PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), > -}; > - > -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = =3D { > - PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), > - PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), > - PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), > - PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), > - PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), > - PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), > - PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), > - PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), > - PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), > - PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), > - PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), > - PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), > - PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), > - PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), > - PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), > - PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), > - PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), > - PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), > - PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), > - PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), > - PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), > - PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), > - PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), > - PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), > - PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), > - PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), > - PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), > - PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)), > - PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), > - PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), > - PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), > - PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), > - PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), > - PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), > - PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), > - PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), > - PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), > - PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), > - PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), > - PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), > - PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), > - PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), > - PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), > - PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), > - PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), > - PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), > - PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), > - PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), > - PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), > - PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), > - PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), > - PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), > - PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), > - PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), > - PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), > - PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), > - PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), > - PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), > -}; > - > -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = =3D { > - PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), > - PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), > - PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), > - PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), > - PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), > - PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), > - PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), > - PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), > - PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), > - PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), > - PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), > - PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), > - PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), > - PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), > - PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), > - PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), > - PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), > - PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), > - PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), > - PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)), > - PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), > - PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), > - PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), > - PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), > - PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), > - PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), > - PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), > - PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), > - PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), > - PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), > - PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), > - PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), > - PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), > - PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), > - PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), > - PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), > - PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), > - PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), > - PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), > - PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), > - PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), > - PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK), > - PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK), > - PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), > - PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), > - PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), > - PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), > - PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), > - PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), > - PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), > - PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), > - PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK), > - PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), > -}; > - > -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = =3D { > - PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), > - PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), > - PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), > - PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), > - PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), > - PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), > - PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), > - PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), > - PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), > - PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), > - PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), > - PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), > - PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), > - PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), > - PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), > - PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), > - PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), > - PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), > - PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), > - PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), > - PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), > - PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), > - PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), > - PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), > - PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), > - PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), > - PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), > - PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)), > - PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), > - PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), > - PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), > - PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), > - PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), > - PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), > - PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), > - PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), > - PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), > - PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), > - PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), > - PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), > - PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), > - PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), > - PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), > - PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), > - PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), > - PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), > - PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), > - PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), > - PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), > - PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), > - PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), > - PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), > - PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), > - PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), > - PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), > - PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), > - PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), > - PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), > -}; > - > -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = =3D { > - PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), > - PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), > - PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), > - PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), > - PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), > - PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), > - PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), > - PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), > - PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), > - PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), > - PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), > - PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), > - PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), > - PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), > - PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), > - PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), > - PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), > - PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), > - PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), > - PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)), > - PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), > - PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), > - PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), > - PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), > - PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), > - PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), > - PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), > - PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), > - PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), > - PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), > - PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), > - PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), > - PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), > - PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), > - PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), > - PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), > - PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), > - PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), > - PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), > - PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), > - PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), > - PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK), > - PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK), > - PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), > - PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), > - PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), > - PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), > - PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), > - PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), > - PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), > - PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), > - PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK), > - PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), > -}; > - > -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = =3D { > - PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), > - PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), > - PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), > - PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), > - PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), > - PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), > - PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), > - PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), > - PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), > - PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), > - PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), > - PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), > - PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), > - PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), > - PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), > - PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), > - PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), > - PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), > - PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), > - PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), > - PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), > - PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), > - PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), > - PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), > - PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), > - PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), > - PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), > - PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)), > - PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), > - PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), > - PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), > - PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), > - PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), > - PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), > - PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), > - PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), > - PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), > - PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), > - PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), > - PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), > - PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), > - PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), > - PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), > - PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), > - PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), > - PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), > - PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), > - PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), > - PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), > - PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), > - PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), > - PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), > - PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), > - PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), > - PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), > - PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), > - PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), > - PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), > -}; > - > -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = =3D { > - PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), > - PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), > - PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), > - PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), > - PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), > - PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), > - PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), > - PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), > - PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), > - PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), > - PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), > - PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), > - PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), > - PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), > - PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), > - PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), > - PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), > - PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), > - PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), > - PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)), > - PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), > - PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), > - PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), > - PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), > - PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), > - PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), > - PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), > - PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), > - PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), > - PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), > - PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), > - PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), > - PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), > - PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), > - PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), > - PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), > - PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), > - PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), > - PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), > - PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), > - PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), > - PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK), > - PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK), > - PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), > - PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), > - PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), > - PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), > - PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), > - PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), > - PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), > - PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), > - PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK), > - PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), > -}; > - > -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[= ] =3D { > - PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), > - PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), > - PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), > -}; > - > -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[= ] =3D { > - PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), > - PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), > -}; > - > static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_de= v, > struct pinctrl_gpio_range *range, > int pin) > @@ -2606,6 +318,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha= _pinctrl *pinctrl, > struct platform_device *pdev) > { > struct airoha_pinctrl_gpiochip *chip =3D &pinctrl->gpiochip; > + struct irq_chip *irq_chip =3D &pinctrl->gpio_irq_chip; > struct gpio_chip *gc =3D &chip->chip; > struct gpio_irq_chip *girq =3D &gc->irq; > struct device *dev =3D &pdev->dev; > @@ -2630,9 +343,11 @@ static int airoha_pinctrl_add_gpiochip(struct airoh= a_pinctrl *pinctrl, > gc->base =3D -1; > gc->ngpio =3D AIROHA_NUM_PINS; > =20 > + memcpy(irq_chip, &airoha_gpio_irq_chip, sizeof(struct irq_chip)); > + > girq->default_type =3D IRQ_TYPE_NONE; > girq->handler =3D handle_bad_irq; > - gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip); > + gpio_irq_chip_set_chip(girq, irq_chip); > =20 > irq =3D platform_get_irq(pdev, 0); > if (irq < 0) > @@ -3011,7 +726,7 @@ static const struct pinctrl_ops airoha_pctlops =3D { > .dt_free_map =3D pinconf_generic_dt_free_map, > }; > =20 > -static int airoha_pinctrl_probe(struct platform_device *pdev) > +int airoha_pinctrl_probe(struct platform_device *pdev) > { > const struct airoha_pinctrl_match_data *data; > struct device *dev =3D &pdev->dev; > @@ -3020,6 +735,8 @@ static int airoha_pinctrl_probe(struct platform_devi= ce *pdev) > int err, i; > =20 > data =3D device_get_match_data(dev); > + if (!data) > + return -EINVAL; > =20 > pinctrl =3D devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL); > if (!pinctrl) > @@ -3036,8 +753,8 @@ static int airoha_pinctrl_probe(struct platform_devi= ce *pdev) > pinctrl->chip_scu =3D map; > =20 > /* Init pinctrl desc struct */ > - pinctrl->desc.name =3D KBUILD_MODNAME; > - pinctrl->desc.owner =3D THIS_MODULE; > + pinctrl->desc.name =3D data->pinctrl_name; > + pinctrl->desc.owner =3D data->pinctrl_owner; > pinctrl->desc.pctlops =3D &airoha_pctlops; > pinctrl->desc.pmxops =3D &airoha_pmxops; > pinctrl->desc.confops =3D &airoha_confops; > @@ -3089,87 +806,10 @@ static int airoha_pinctrl_probe(struct platform_de= vice *pdev) > /* build gpio-chip */ > return airoha_pinctrl_add_gpiochip(pinctrl, pdev); > } > - > -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = =3D { > - .pins =3D en7581_pinctrl_pins, > - .num_pins =3D ARRAY_SIZE(en7581_pinctrl_pins), > - .grps =3D en7581_pinctrl_groups, > - .num_grps =3D ARRAY_SIZE(en7581_pinctrl_groups), > - .funcs =3D en7581_pinctrl_funcs, > - .num_funcs =3D ARRAY_SIZE(en7581_pinctrl_funcs), > - .confs_info =3D { > - [AIROHA_PINCTRL_CONFS_PULLUP] =3D { > - .confs =3D en7581_pinctrl_pullup_conf, > - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pullup_conf), > - }, > - [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { > - .confs =3D en7581_pinctrl_pulldown_conf, > - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pulldown_conf), > - }, > - [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { > - .confs =3D en7581_pinctrl_drive_e2_conf, > - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), > - }, > - [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { > - .confs =3D en7581_pinctrl_drive_e4_conf, > - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), > - }, > - [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] =3D { > - .confs =3D en7581_pinctrl_pcie_rst_od_conf, > - .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), > - }, > - }, > -}; > - > -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = =3D { > - .pins =3D an7583_pinctrl_pins, > - .num_pins =3D ARRAY_SIZE(an7583_pinctrl_pins), > - .grps =3D an7583_pinctrl_groups, > - .num_grps =3D ARRAY_SIZE(an7583_pinctrl_groups), > - .funcs =3D an7583_pinctrl_funcs, > - .num_funcs =3D ARRAY_SIZE(an7583_pinctrl_funcs), > - .confs_info =3D { > - [AIROHA_PINCTRL_CONFS_PULLUP] =3D { > - .confs =3D an7583_pinctrl_pullup_conf, > - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pullup_conf), > - }, > - [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { > - .confs =3D an7583_pinctrl_pulldown_conf, > - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pulldown_conf), > - }, > - [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { > - .confs =3D an7583_pinctrl_drive_e2_conf, > - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), > - }, > - [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { > - .confs =3D an7583_pinctrl_drive_e4_conf, > - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), > - }, > - [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] =3D { > - .confs =3D an7583_pinctrl_pcie_rst_od_conf, > - .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf), > - }, > - }, > -}; > - > -static const struct of_device_id airoha_pinctrl_of_match[] =3D { > - { .compatible =3D "airoha,en7581-pinctrl", .data =3D &en7581_pinctrl_ma= tch_data }, > - { .compatible =3D "airoha,an7583-pinctrl", .data =3D &an7583_pinctrl_ma= tch_data }, > - { /* sentinel */ } > -}; > -MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); > - > -static struct platform_driver airoha_pinctrl_driver =3D { > - .probe =3D airoha_pinctrl_probe, > - .driver =3D { > - .name =3D "pinctrl-airoha", > - .of_match_table =3D airoha_pinctrl_of_match, > - }, > -}; > -module_platform_driver(airoha_pinctrl_driver); > +EXPORT_SYMBOL_GPL(airoha_pinctrl_probe); > =20 > MODULE_LICENSE("GPL"); > MODULE_AUTHOR("Lorenzo Bianconi "); > MODULE_AUTHOR("Benjamin Larsson "); > MODULE_AUTHOR("Markus Gothe "); > -MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC"); > +MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC"); > diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/ai= roha/pinctrl-an7581.c > new file mode 100644 > index 0000000000000..522b35bbaa121 > --- /dev/null > +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c > @@ -0,0 +1,1486 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Author: Lorenzo Bianconi > + * Author: Benjamin Larsson > + * Author: Markus Gothe > + */ > + > +#include "airoha-common.h" > + > +/* MUX */ > +#define REG_GPIO_2ND_I2C_MODE 0x0214 > +#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14) > +#define GPIO_I2C_MASTER_MODE_MODE BIT(13) > +#define GPIO_I2S_MODE_MASK BIT(12) > +#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) > +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) > +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) > +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) > +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) > +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) > +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) > +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) > +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) > +#define PON_TOD_1PPS_MODE_MASK BIT(2) > +#define GSW_TOD_1PPS_MODE_MASK BIT(1) > +#define GPIO_2ND_I2C_MODE_MASK BIT(0) > + > +#define REG_GPIO_SPI_CS1_MODE 0x0218 > +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) > +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) > +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) > +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) > +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) > +#define GPIO_PCM_SPI_MODE_MASK BIT(16) > +#define GPIO_PCM2_MODE_MASK BIT(13) > +#define GPIO_PCM1_MODE_MASK BIT(12) > +#define GPIO_PCM_INT_MODE_MASK BIT(9) > +#define GPIO_PCM_RESET_MODE_MASK BIT(8) > +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) > +#define GPIO_SPI_CS4_MODE_MASK BIT(3) > +#define GPIO_SPI_CS3_MODE_MASK BIT(2) > +#define GPIO_SPI_CS2_MODE_MASK BIT(1) > +#define GPIO_SPI_CS1_MODE_MASK BIT(0) > + > +#define REG_GPIO_PON_MODE 0x021c > +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) > +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) > +#define GPIO_PCIE_RESET2_MASK BIT(12) > +#define SIPO_RCLK_MODE_MASK BIT(11) > +#define GPIO_PCIE_RESET1_MASK BIT(10) > +#define GPIO_PCIE_RESET0_MASK BIT(9) > +#define GPIO_UART5_MODE_MASK BIT(8) > +#define GPIO_UART4_MODE_MASK BIT(7) > +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) > +#define GPIO_HSUART_MODE_MASK BIT(5) > +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) > +#define GPIO_UART2_MODE_MASK BIT(3) > +#define GPIO_SIPO_MODE_MASK BIT(2) > +#define GPIO_EMMC_MODE_MASK BIT(1) > +#define GPIO_PON_MODE_MASK BIT(0) > + > +#define REG_NPU_UART_EN 0x0224 > +#define JTAG_UDI_EN_MASK BIT(4) > +#define JTAG_DFD_EN_MASK BIT(3) > + > +#define REG_FORCE_GPIO_EN 0x0228 > +#define FORCE_GPIO_EN(n) BIT(n) > + > +/* LED MAP */ > +#define REG_LAN_LED0_MAPPING 0x027c > +#define REG_LAN_LED1_MAPPING 0x0280 > + > +#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) > +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (= _n)) > + > +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) > +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (= _n)) > + > +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) > +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (= _n)) > + > +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) > +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (= _n)) > + > +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) > +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (= _n)) > + > +/* CONF */ > +#define REG_I2C_SDA_E2 0x001c > +#define SPI_MISO_E2_MASK BIT(14) > +#define SPI_MOSI_E2_MASK BIT(13) > +#define SPI_CLK_E2_MASK BIT(12) > +#define SPI_CS0_E2_MASK BIT(11) > +#define PCIE2_RESET_E2_MASK BIT(10) > +#define PCIE1_RESET_E2_MASK BIT(9) > +#define PCIE0_RESET_E2_MASK BIT(8) > +#define UART1_RXD_E2_MASK BIT(3) > +#define UART1_TXD_E2_MASK BIT(2) > +#define I2C_SCL_E2_MASK BIT(1) > +#define I2C_SDA_E2_MASK BIT(0) > + > +#define REG_I2C_SDA_E4 0x0020 > +#define SPI_MISO_E4_MASK BIT(14) > +#define SPI_MOSI_E4_MASK BIT(13) > +#define SPI_CLK_E4_MASK BIT(12) > +#define SPI_CS0_E4_MASK BIT(11) > +#define PCIE2_RESET_E4_MASK BIT(10) > +#define PCIE1_RESET_E4_MASK BIT(9) > +#define PCIE0_RESET_E4_MASK BIT(8) > +#define UART1_RXD_E4_MASK BIT(3) > +#define UART1_TXD_E4_MASK BIT(2) > +#define I2C_SCL_E4_MASK BIT(1) > +#define I2C_SDA_E4_MASK BIT(0) > + > +#define REG_GPIO_L_E2 0x0024 > +#define REG_GPIO_L_E4 0x0028 > +#define REG_GPIO_H_E2 0x002c > +#define REG_GPIO_H_E4 0x0030 > + > +#define REG_I2C_SDA_PU 0x0044 > +#define SPI_MISO_PU_MASK BIT(14) > +#define SPI_MOSI_PU_MASK BIT(13) > +#define SPI_CLK_PU_MASK BIT(12) > +#define SPI_CS0_PU_MASK BIT(11) > +#define PCIE2_RESET_PU_MASK BIT(10) > +#define PCIE1_RESET_PU_MASK BIT(9) > +#define PCIE0_RESET_PU_MASK BIT(8) > +#define UART1_RXD_PU_MASK BIT(3) > +#define UART1_TXD_PU_MASK BIT(2) > +#define I2C_SCL_PU_MASK BIT(1) > +#define I2C_SDA_PU_MASK BIT(0) > + > +#define REG_I2C_SDA_PD 0x0048 > +#define SPI_MISO_PD_MASK BIT(14) > +#define SPI_MOSI_PD_MASK BIT(13) > +#define SPI_CLK_PD_MASK BIT(12) > +#define SPI_CS0_PD_MASK BIT(11) > +#define PCIE2_RESET_PD_MASK BIT(10) > +#define PCIE1_RESET_PD_MASK BIT(9) > +#define PCIE0_RESET_PD_MASK BIT(8) > +#define UART1_RXD_PD_MASK BIT(3) > +#define UART1_TXD_PD_MASK BIT(2) > +#define I2C_SCL_PD_MASK BIT(1) > +#define I2C_SDA_PD_MASK BIT(0) > + > +#define REG_GPIO_L_PU 0x004c > +#define REG_GPIO_L_PD 0x0050 > +#define REG_GPIO_H_PU 0x0054 > +#define REG_GPIO_H_PD 0x0058 > + > +#define REG_PCIE_RESET_OD 0x018c > +#define PCIE2_RESET_OD_MASK BIT(2) > +#define PCIE1_RESET_OD_MASK BIT(1) > +#define PCIE0_RESET_OD_MASK BIT(0) > + > +/* PWM MODE CONF */ > +#define REG_GPIO_FLASH_MODE_CFG 0x0034 > +#define GPIO15_FLASH_MODE_CFG BIT(15) > +#define GPIO14_FLASH_MODE_CFG BIT(14) > +#define GPIO13_FLASH_MODE_CFG BIT(13) > +#define GPIO12_FLASH_MODE_CFG BIT(12) > +#define GPIO11_FLASH_MODE_CFG BIT(11) > +#define GPIO10_FLASH_MODE_CFG BIT(10) > +#define GPIO9_FLASH_MODE_CFG BIT(9) > +#define GPIO8_FLASH_MODE_CFG BIT(8) > +#define GPIO7_FLASH_MODE_CFG BIT(7) > +#define GPIO6_FLASH_MODE_CFG BIT(6) > +#define GPIO5_FLASH_MODE_CFG BIT(5) > +#define GPIO4_FLASH_MODE_CFG BIT(4) > +#define GPIO3_FLASH_MODE_CFG BIT(3) > +#define GPIO2_FLASH_MODE_CFG BIT(2) > +#define GPIO1_FLASH_MODE_CFG BIT(1) > +#define GPIO0_FLASH_MODE_CFG BIT(0) > + > +/* PWM MODE CONF EXT */ > +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 > +#define GPIO51_FLASH_MODE_CFG BIT(31) > +#define GPIO50_FLASH_MODE_CFG BIT(30) > +#define GPIO49_FLASH_MODE_CFG BIT(29) > +#define GPIO48_FLASH_MODE_CFG BIT(28) > +#define GPIO47_FLASH_MODE_CFG BIT(27) > +#define GPIO46_FLASH_MODE_CFG BIT(26) > +#define GPIO45_FLASH_MODE_CFG BIT(25) > +#define GPIO44_FLASH_MODE_CFG BIT(24) > +#define GPIO43_FLASH_MODE_CFG BIT(23) > +#define GPIO42_FLASH_MODE_CFG BIT(22) > +#define GPIO41_FLASH_MODE_CFG BIT(21) > +#define GPIO40_FLASH_MODE_CFG BIT(20) > +#define GPIO39_FLASH_MODE_CFG BIT(19) > +#define GPIO38_FLASH_MODE_CFG BIT(18) > +#define GPIO37_FLASH_MODE_CFG BIT(17) > +#define GPIO36_FLASH_MODE_CFG BIT(16) > +#define GPIO31_FLASH_MODE_CFG BIT(15) > +#define GPIO30_FLASH_MODE_CFG BIT(14) > +#define GPIO29_FLASH_MODE_CFG BIT(13) > +#define GPIO28_FLASH_MODE_CFG BIT(12) > +#define GPIO27_FLASH_MODE_CFG BIT(11) > +#define GPIO26_FLASH_MODE_CFG BIT(10) > +#define GPIO25_FLASH_MODE_CFG BIT(9) > +#define GPIO24_FLASH_MODE_CFG BIT(8) > +#define GPIO23_FLASH_MODE_CFG BIT(7) > +#define GPIO22_FLASH_MODE_CFG BIT(6) > +#define GPIO21_FLASH_MODE_CFG BIT(5) > +#define GPIO20_FLASH_MODE_CFG BIT(4) > +#define GPIO19_FLASH_MODE_CFG BIT(3) > +#define GPIO18_FLASH_MODE_CFG BIT(2) > +#define GPIO17_FLASH_MODE_CFG BIT(1) > +#define GPIO16_FLASH_MODE_CFG BIT(0) > + > +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_GPIO_PON_MODE, \ > + (mux_val), \ > + (mux_val) \ > + }, \ > + .regmap_size =3D 1, \ > + } > + > +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_PWM_EXT_MUX, \ > + REG_GPIO_FLASH_MODE_CFG_EXT, \ > + (mux_val), \ > + 0 \ > + }, \ > + .regmap[1] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_GPIO_PON_MODE, \ > + (smux_val), \ > + (smux_val) \ > + }, \ > + .regmap_size =3D 2, \ > + } > + > +/* PWM */ > +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_PWM_MUX, \ > + REG_GPIO_FLASH_MODE_CFG, \ > + (mux_val), \ > + (mux_val) \ > + }, \ > + .regmap_size =3D 1, \ > + } > + > +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_PWM_EXT_MUX, \ > + REG_GPIO_FLASH_MODE_CFG_EXT, \ > + (mux_val), \ > + (mux_val) \ > + }, \ > + .regmap_size =3D 1, \ > + } > + > +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_PWM_EXT_MUX, \ > + REG_GPIO_FLASH_MODE_CFG_EXT, \ > + (mux_val), \ > + (mux_val) \ > + }, \ > + .regmap[1] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_GPIO_PON_MODE, \ > + (smux_val), \ > + (smux_val) \ > + }, \ > + .regmap_size =3D 2, \ > + } > + > +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_GPIO_2ND_I2C_MODE, \ > + (mux_val), \ > + (mux_val), \ > + }, \ > + .regmap[1] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_LAN_LED0_MAPPING, \ > + (map_mask), \ > + (map_val), \ > + }, \ > + .regmap_size =3D 2, \ > + } > + > +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_GPIO_2ND_I2C_MODE, \ > + (mux_val), \ > + (mux_val), \ > + }, \ > + .regmap[1] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_LAN_LED1_MAPPING, \ > + (map_mask), \ > + (map_val), \ > + }, \ > + .regmap_size =3D 2, \ > + } > + > +static struct pinctrl_pin_desc en7581_pinctrl_pins[] =3D { > + PINCTRL_PIN(0, "uart1_txd"), > + PINCTRL_PIN(1, "uart1_rxd"), > + PINCTRL_PIN(2, "i2c_scl"), > + PINCTRL_PIN(3, "i2c_sda"), > + PINCTRL_PIN(4, "spi_cs0"), > + PINCTRL_PIN(5, "spi_clk"), > + PINCTRL_PIN(6, "spi_mosi"), > + PINCTRL_PIN(7, "spi_miso"), > + PINCTRL_PIN(13, "gpio0"), > + PINCTRL_PIN(14, "gpio1"), > + PINCTRL_PIN(15, "gpio2"), > + PINCTRL_PIN(16, "gpio3"), > + PINCTRL_PIN(17, "gpio4"), > + PINCTRL_PIN(18, "gpio5"), > + PINCTRL_PIN(19, "gpio6"), > + PINCTRL_PIN(20, "gpio7"), > + PINCTRL_PIN(21, "gpio8"), > + PINCTRL_PIN(22, "gpio9"), > + PINCTRL_PIN(23, "gpio10"), > + PINCTRL_PIN(24, "gpio11"), > + PINCTRL_PIN(25, "gpio12"), > + PINCTRL_PIN(26, "gpio13"), > + PINCTRL_PIN(27, "gpio14"), > + PINCTRL_PIN(28, "gpio15"), > + PINCTRL_PIN(29, "gpio16"), > + PINCTRL_PIN(30, "gpio17"), > + PINCTRL_PIN(31, "gpio18"), > + PINCTRL_PIN(32, "gpio19"), > + PINCTRL_PIN(33, "gpio20"), > + PINCTRL_PIN(34, "gpio21"), > + PINCTRL_PIN(35, "gpio22"), > + PINCTRL_PIN(36, "gpio23"), > + PINCTRL_PIN(37, "gpio24"), > + PINCTRL_PIN(38, "gpio25"), > + PINCTRL_PIN(39, "gpio26"), > + PINCTRL_PIN(40, "gpio27"), > + PINCTRL_PIN(41, "gpio28"), > + PINCTRL_PIN(42, "gpio29"), > + PINCTRL_PIN(43, "gpio30"), > + PINCTRL_PIN(44, "gpio31"), > + PINCTRL_PIN(45, "gpio32"), > + PINCTRL_PIN(46, "gpio33"), > + PINCTRL_PIN(47, "gpio34"), > + PINCTRL_PIN(48, "gpio35"), > + PINCTRL_PIN(49, "gpio36"), > + PINCTRL_PIN(50, "gpio37"), > + PINCTRL_PIN(51, "gpio38"), > + PINCTRL_PIN(52, "gpio39"), > + PINCTRL_PIN(53, "gpio40"), > + PINCTRL_PIN(54, "gpio41"), > + PINCTRL_PIN(55, "gpio42"), > + PINCTRL_PIN(56, "gpio43"), > + PINCTRL_PIN(57, "gpio44"), > + PINCTRL_PIN(58, "gpio45"), > + PINCTRL_PIN(59, "gpio46"), > + PINCTRL_PIN(60, "pcie_reset0"), > + PINCTRL_PIN(61, "pcie_reset1"), > + PINCTRL_PIN(62, "pcie_reset2"), > +}; > + > +static const int en7581_pon_pins[] =3D { 49, 50, 51, 52, 53, 54 }; > +static const int en7581_pon_tod_1pps_pins[] =3D { 46 }; > +static const int en7581_gsw_tod_1pps_pins[] =3D { 46 }; > +static const int en7581_sipo_pins[] =3D { 16, 17 }; > +static const int en7581_sipo_rclk_pins[] =3D { 16, 17, 43 }; > +static const int en7581_mdio_pins[] =3D { 14, 15 }; > +static const int en7581_uart2_pins[] =3D { 48, 55 }; > +static const int en7581_uart2_cts_rts_pins[] =3D { 46, 47 }; > +static const int en7581_hsuart_pins[] =3D { 28, 29 }; > +static const int en7581_hsuart_cts_rts_pins[] =3D { 26, 27 }; > +static const int en7581_uart4_pins[] =3D { 38, 39 }; > +static const int en7581_uart5_pins[] =3D { 18, 19 }; > +static const int en7581_i2c0_pins[] =3D { 2, 3 }; > +static const int en7581_i2c1_pins[] =3D { 14, 15 }; > +static const int en7581_jtag_udi_pins[] =3D { 16, 17, 18, 19, 20 }; > +static const int en7581_jtag_dfd_pins[] =3D { 16, 17, 18, 19, 20 }; > +static const int en7581_i2s_pins[] =3D { 26, 27, 28, 29 }; > +static const int en7581_pcm1_pins[] =3D { 22, 23, 24, 25 }; > +static const int en7581_pcm2_pins[] =3D { 18, 19, 20, 21 }; > +static const int en7581_spi_quad_pins[] =3D { 32, 33 }; > +static const int en7581_spi_pins[] =3D { 4, 5, 6, 7 }; > +static const int en7581_spi_cs1_pins[] =3D { 34 }; > +static const int en7581_pcm_spi_pins[] =3D { 18, 19, 20, 21, 22, 23, 24,= 25 }; > +static const int en7581_pcm_spi_int_pins[] =3D { 14 }; > +static const int en7581_pcm_spi_rst_pins[] =3D { 15 }; > +static const int en7581_pcm_spi_cs1_pins[] =3D { 43 }; > +static const int en7581_pcm_spi_cs2_pins[] =3D { 40 }; > +static const int en7581_pcm_spi_cs2_p128_pins[] =3D { 40 }; > +static const int en7581_pcm_spi_cs2_p156_pins[] =3D { 40 }; > +static const int en7581_pcm_spi_cs3_pins[] =3D { 41 }; > +static const int en7581_pcm_spi_cs4_pins[] =3D { 42 }; > +static const int en7581_emmc_pins[] =3D { > + 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 > +}; > +static const int en7581_pnand_pins[] =3D { > + 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 > +}; > +static const int en7581_gpio0_pins[] =3D { 13 }; > +static const int en7581_gpio1_pins[] =3D { 14 }; > +static const int en7581_gpio2_pins[] =3D { 15 }; > +static const int en7581_gpio3_pins[] =3D { 16 }; > +static const int en7581_gpio4_pins[] =3D { 17 }; > +static const int en7581_gpio5_pins[] =3D { 18 }; > +static const int en7581_gpio6_pins[] =3D { 19 }; > +static const int en7581_gpio7_pins[] =3D { 20 }; > +static const int en7581_gpio8_pins[] =3D { 21 }; > +static const int en7581_gpio9_pins[] =3D { 22 }; > +static const int en7581_gpio10_pins[] =3D { 23 }; > +static const int en7581_gpio11_pins[] =3D { 24 }; > +static const int en7581_gpio12_pins[] =3D { 25 }; > +static const int en7581_gpio13_pins[] =3D { 26 }; > +static const int en7581_gpio14_pins[] =3D { 27 }; > +static const int en7581_gpio15_pins[] =3D { 28 }; > +static const int en7581_gpio16_pins[] =3D { 29 }; > +static const int en7581_gpio17_pins[] =3D { 30 }; > +static const int en7581_gpio18_pins[] =3D { 31 }; > +static const int en7581_gpio19_pins[] =3D { 32 }; > +static const int en7581_gpio20_pins[] =3D { 33 }; > +static const int en7581_gpio21_pins[] =3D { 34 }; > +static const int en7581_gpio22_pins[] =3D { 35 }; > +static const int en7581_gpio23_pins[] =3D { 36 }; > +static const int en7581_gpio24_pins[] =3D { 37 }; > +static const int en7581_gpio25_pins[] =3D { 38 }; > +static const int en7581_gpio26_pins[] =3D { 39 }; > +static const int en7581_gpio27_pins[] =3D { 40 }; > +static const int en7581_gpio28_pins[] =3D { 41 }; > +static const int en7581_gpio29_pins[] =3D { 42 }; > +static const int en7581_gpio30_pins[] =3D { 43 }; > +static const int en7581_gpio31_pins[] =3D { 44 }; > +static const int en7581_gpio32_pins[] =3D { 45 }; > +static const int en7581_gpio33_pins[] =3D { 46 }; > +static const int en7581_gpio34_pins[] =3D { 47 }; > +static const int en7581_gpio35_pins[] =3D { 48 }; > +static const int en7581_gpio36_pins[] =3D { 49 }; > +static const int en7581_gpio37_pins[] =3D { 50 }; > +static const int en7581_gpio38_pins[] =3D { 51 }; > +static const int en7581_gpio39_pins[] =3D { 52 }; > +static const int en7581_gpio40_pins[] =3D { 53 }; > +static const int en7581_gpio41_pins[] =3D { 54 }; > +static const int en7581_gpio42_pins[] =3D { 55 }; > +static const int en7581_gpio43_pins[] =3D { 56 }; > +static const int en7581_gpio44_pins[] =3D { 57 }; > +static const int en7581_gpio45_pins[] =3D { 58 }; > +static const int en7581_gpio46_pins[] =3D { 59 }; > +static const int en7581_gpio47_pins[] =3D { 60 }; > +static const int en7581_gpio48_pins[] =3D { 61 }; > +static const int en7581_gpio49_pins[] =3D { 62 }; > +static const int en7581_pcie_reset0_pins[] =3D { 60 }; > +static const int en7581_pcie_reset1_pins[] =3D { 61 }; > +static const int en7581_pcie_reset2_pins[] =3D { 62 }; > + > +static const struct pingroup en7581_pinctrl_groups[] =3D { > + PINCTRL_PIN_GROUP("pon", en7581_pon), > + PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), > + PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), > + PINCTRL_PIN_GROUP("sipo", en7581_sipo), > + PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), > + PINCTRL_PIN_GROUP("mdio", en7581_mdio), > + PINCTRL_PIN_GROUP("uart2", en7581_uart2), > + PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), > + PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), > + PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), > + PINCTRL_PIN_GROUP("uart4", en7581_uart4), > + PINCTRL_PIN_GROUP("uart5", en7581_uart5), > + PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), > + PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), > + PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), > + PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), > + PINCTRL_PIN_GROUP("i2s", en7581_i2s), > + PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), > + PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), > + PINCTRL_PIN_GROUP("spi", en7581_spi), > + PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), > + PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), > + PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), > + PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), > + PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), > + PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), > + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), > + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), > + PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), > + PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), > + PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), > + PINCTRL_PIN_GROUP("emmc", en7581_emmc), > + PINCTRL_PIN_GROUP("pnand", en7581_pnand), > + PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), > + PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), > + PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), > + PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), > + PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), > + PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), > + PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), > + PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), > + PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), > + PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), > + PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), > + PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), > + PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), > + PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), > + PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), > + PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), > + PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), > + PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), > + PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), > + PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), > + PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), > + PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), > + PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), > + PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), > + PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), > + PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), > + PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), > + PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), > + PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), > + PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), > + PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), > + PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), > + PINCTRL_PIN_GROUP("gpio32", en7581_gpio32), > + PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), > + PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), > + PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), > + PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), > + PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), > + PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), > + PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), > + PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), > + PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), > + PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), > + PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), > + PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), > + PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), > + PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), > + PINCTRL_PIN_GROUP("gpio47", en7581_gpio47), > + PINCTRL_PIN_GROUP("gpio48", en7581_gpio48), > + PINCTRL_PIN_GROUP("gpio49", en7581_gpio49), > + PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), > + PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), > + PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), > +}; > + > +static const char *const pon_groups[] =3D { "pon" }; > +static const char *const tod_1pps_groups[] =3D { > + "pon_tod_1pps", "gsw_tod_1pps" > +}; > +static const char *const sipo_groups[] =3D { "sipo", "sipo_rclk" }; > +static const char *const mdio_groups[] =3D { "mdio" }; > +static const char *const uart_groups[] =3D { > + "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", > + "uart4", "uart5" > +}; > +static const char *const i2c_groups[] =3D { "i2c1" }; > +static const char *const jtag_groups[] =3D { "jtag_udi", "jtag_dfd" }; > +static const char *const pcm_groups[] =3D { "pcm1", "pcm2" }; > +static const char *const spi_groups[] =3D { "spi_quad", "spi_cs1" }; > +static const char *const pcm_spi_groups[] =3D { > + "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1", > + "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", > + "pcm_spi_cs4" > +}; > +static const char *const i2s_groups[] =3D { "i2s" }; > +static const char *const emmc_groups[] =3D { "emmc" }; > +static const char *const pnand_groups[] =3D { "pnand" }; > +static const char *const gpio_groups[] =3D { "gpio47", "gpio48", "gpio49= " }; > +static const char *const pcie_reset_groups[] =3D { > + "pcie_reset0", "pcie_reset1", "pcie_reset2" > +}; > +static const char *const pwm_groups[] =3D { > + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", > + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", > + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", > + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", > + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", > + "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39", > + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", > + "gpio46", "gpio47", "gpio48", "gpio49" > +}; > +static const char *const phy1_led0_groups[] =3D { > + "gpio33", "gpio34", "gpio35", "gpio42" > +}; > +static const char *const phy2_led0_groups[] =3D { > + "gpio33", "gpio34", "gpio35", "gpio42" > +}; > +static const char *const phy3_led0_groups[] =3D { > + "gpio33", "gpio34", "gpio35", "gpio42" > +}; > +static const char *const phy4_led0_groups[] =3D { > + "gpio33", "gpio34", "gpio35", "gpio42" > +}; > +static const char *const phy1_led1_groups[] =3D { > + "gpio43", "gpio44", "gpio45", "gpio46" > +}; > +static const char *const phy2_led1_groups[] =3D { > + "gpio43", "gpio44", "gpio45", "gpio46" > +}; > +static const char *const phy3_led1_groups[] =3D { > + "gpio43", "gpio44", "gpio45", "gpio46" > +}; > +static const char *const phy4_led1_groups[] =3D { > + "gpio43", "gpio44", "gpio45", "gpio46" > +}; > + > +static const struct airoha_pinctrl_func_group pon_func_group[] =3D { > + { > + .name =3D "pon", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_PON_MODE_MASK, > + GPIO_PON_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] =3D { > + { > + .name =3D "pon_tod_1pps", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_2ND_I2C_MODE, > + PON_TOD_1PPS_MODE_MASK, > + PON_TOD_1PPS_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "gsw_tod_1pps", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_2ND_I2C_MODE, > + GSW_TOD_1PPS_MODE_MASK, > + GSW_TOD_1PPS_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group sipo_func_group[] =3D { > + { > + .name =3D "sipo", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, > + GPIO_SIPO_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "sipo_rclk", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, > + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group mdio_func_group[] =3D { > + { > + .name =3D "mdio", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_2ND_I2C_MODE, > + GPIO_MDC_IO_MASTER_MODE_MASK, > + GPIO_MDC_IO_MASTER_MODE_MASK > + }, > + .regmap[1] =3D { > + AIROHA_FUNC_MUX, > + REG_FORCE_GPIO_EN, > + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), > + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) > + }, > + .regmap_size =3D 2, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group uart_func_group[] =3D { > + { > + .name =3D "uart2", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_UART2_MODE_MASK, > + GPIO_UART2_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "uart2_cts_rts", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, > + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "hsuart", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, > + GPIO_HSUART_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > + { > + .name =3D "hsuart_cts_rts", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, > + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "uart4", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_UART4_MODE_MASK, > + GPIO_UART4_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "uart5", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_UART5_MODE_MASK, > + GPIO_UART5_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group i2c_func_group[] =3D { > + { > + .name =3D "i2c1", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_2ND_I2C_MODE, > + GPIO_2ND_I2C_MODE_MASK, > + GPIO_2ND_I2C_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group jtag_func_group[] =3D { > + { > + .name =3D "jtag_udi", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_NPU_UART_EN, > + JTAG_UDI_EN_MASK, > + JTAG_UDI_EN_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "jtag_dfd", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_NPU_UART_EN, > + JTAG_DFD_EN_MASK, > + JTAG_DFD_EN_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group pcm_func_group[] =3D { > + { > + .name =3D "pcm1", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM1_MODE_MASK, > + GPIO_PCM1_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm2", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM2_MODE_MASK, > + GPIO_PCM2_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group spi_func_group[] =3D { > + { > + .name =3D "spi_quad", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_SPI_QUAD_MODE_MASK, > + GPIO_SPI_QUAD_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "spi_cs1", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_SPI_CS1_MODE_MASK, > + GPIO_SPI_CS1_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "spi_cs2", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_SPI_CS2_MODE_MASK, > + GPIO_SPI_CS2_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "spi_cs3", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_SPI_CS3_MODE_MASK, > + GPIO_SPI_CS3_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "spi_cs4", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_SPI_CS4_MODE_MASK, > + GPIO_SPI_CS4_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] =3D { > + { > + .name =3D "pcm_spi", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_SPI_MODE_MASK, > + GPIO_PCM_SPI_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_int", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_INT_MODE_MASK, > + GPIO_PCM_INT_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_rst", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_RESET_MODE_MASK, > + GPIO_PCM_RESET_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_cs1", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_SPI_CS1_MODE_MASK, > + GPIO_PCM_SPI_CS1_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_cs2_p128", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_SPI_CS2_MODE_P128_MASK, > + GPIO_PCM_SPI_CS2_MODE_P128_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_cs2_p156", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_SPI_CS2_MODE_P156_MASK, > + GPIO_PCM_SPI_CS2_MODE_P156_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_cs3", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_SPI_CS3_MODE_MASK, > + GPIO_PCM_SPI_CS3_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_cs4", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_SPI_CS4_MODE_MASK, > + GPIO_PCM_SPI_CS4_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group i2s_func_group[] =3D { > + { > + .name =3D "i2s", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_2ND_I2C_MODE, > + GPIO_I2S_MODE_MASK, > + GPIO_I2S_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group emmc_func_group[] =3D { > + { > + .name =3D "emmc", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_EMMC_MODE_MASK, > + GPIO_EMMC_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group pnand_func_group[] =3D { > + { > + .name =3D "pnand", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_PARALLEL_NAND_MODE_MASK, > + GPIO_PARALLEL_NAND_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group gpio_func_group[] =3D { > + AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, > + GPIO_PCIE_RESET0_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, > + GPIO_PCIE_RESET1_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, > + GPIO_PCIE_RESET2_MASK), > +}; > + > +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = =3D { > + { > + .name =3D "pcie_reset0", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_PCIE_RESET0_MASK, > + 0 > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcie_reset1", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_PCIE_RESET1_MASK, > + 0 > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcie_reset2", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_PCIE_RESET2_MASK, > + 0 > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group pwm_func_group[] =3D { > + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, > + GPIO_PCIE_RESET0_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, > + GPIO_PCIE_RESET1_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, > + GPIO_PCIE_RESET2_MASK), > +}; > + > +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] =3D= { > + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), > +}; > + > +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] =3D= { > + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), > +}; > + > +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] =3D= { > + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), > +}; > + > +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] =3D= { > + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), > +}; > + > +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] =3D= { > + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), > +}; > + > +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] =3D= { > + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), > +}; > + > +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] =3D= { > + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), > +}; > + > +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] =3D= { > + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), > +}; > + > +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] =3D { > + PINCTRL_FUNC_DESC("pon", pon), > + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), > + PINCTRL_FUNC_DESC("sipo", sipo), > + PINCTRL_FUNC_DESC("mdio", mdio), > + PINCTRL_FUNC_DESC("uart", uart), > + PINCTRL_FUNC_DESC("i2c", i2c), > + PINCTRL_FUNC_DESC("jtag", jtag), > + PINCTRL_FUNC_DESC("pcm", pcm), > + PINCTRL_FUNC_DESC("spi", spi), > + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), > + PINCTRL_FUNC_DESC("i2s", i2s), > + PINCTRL_FUNC_DESC("emmc", emmc), > + PINCTRL_FUNC_DESC("pnand", pnand), > + PINCTRL_FUNC_DESC("gpio", gpio), > + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), > + PINCTRL_FUNC_DESC("pwm", pwm), > + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), > + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), > + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), > + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), > + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), > + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), > + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), > + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), > +}; > + > +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] =3D= { > + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), > + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), > + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), > + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), > + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), > + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), > + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), > + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), > + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), > + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), > + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), > + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), > + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), > + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), > + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), > + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), > + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), > + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), > + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), > + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), > + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), > + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), > + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), > + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), > + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), > + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), > + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), > + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)), > + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), > + PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), > + PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), > + PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), > + PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), > + PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), > + PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), > + PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), > + PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), > + PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), > + PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), > + PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), > + PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), > + PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), > + PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), > + PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), > + PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), > + PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), > + PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), > + PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), > + PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), > + PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), > + PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), > + PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), > + PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), > + PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), > + PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), > + PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), > + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), > + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), > +}; > + > +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = =3D { > + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), > + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), > + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), > + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), > + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), > + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), > + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), > + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), > + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), > + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), > + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), > + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), > + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), > + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), > + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), > + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), > + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), > + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), > + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), > + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), > + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), > + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), > + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), > + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), > + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), > + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), > + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), > + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)), > + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), > + PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), > + PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), > + PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), > + PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), > + PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), > + PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), > + PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), > + PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), > + PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), > + PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), > + PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), > + PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), > + PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), > + PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), > + PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), > + PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), > + PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), > + PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), > + PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), > + PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), > + PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), > + PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), > + PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), > + PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), > + PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), > + PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), > + PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), > + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), > + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), > +}; > + > +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = =3D { > + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), > + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), > + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), > + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), > + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), > + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), > + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), > + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), > + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), > + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), > + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), > + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), > + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), > + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), > + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), > + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), > + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), > + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), > + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), > + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), > + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), > + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), > + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), > + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), > + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), > + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), > + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), > + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)), > + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), > + PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), > + PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), > + PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), > + PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), > + PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), > + PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), > + PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), > + PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), > + PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), > + PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), > + PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), > + PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), > + PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), > + PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), > + PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), > + PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), > + PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), > + PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), > + PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), > + PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), > + PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), > + PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), > + PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), > + PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), > + PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), > + PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), > + PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), > + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), > + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), > +}; > + > +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = =3D { > + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), > + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), > + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), > + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), > + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), > + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), > + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), > + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), > + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), > + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), > + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), > + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), > + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), > + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), > + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), > + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), > + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), > + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), > + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), > + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), > + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), > + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), > + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), > + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), > + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), > + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), > + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), > + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)), > + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), > + PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), > + PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), > + PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), > + PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), > + PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), > + PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), > + PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), > + PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), > + PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), > + PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), > + PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), > + PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), > + PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), > + PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), > + PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), > + PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), > + PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), > + PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), > + PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), > + PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), > + PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), > + PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), > + PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), > + PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), > + PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), > + PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), > + PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), > + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), > + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), > +}; > + > +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[= ] =3D { > + PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), > + PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), > + PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), > +}; > + > +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = =3D { > + .pinctrl_name =3D KBUILD_MODNAME, > + .pinctrl_owner =3D THIS_MODULE, > + .pins =3D en7581_pinctrl_pins, > + .num_pins =3D ARRAY_SIZE(en7581_pinctrl_pins), > + .grps =3D en7581_pinctrl_groups, > + .num_grps =3D ARRAY_SIZE(en7581_pinctrl_groups), > + .funcs =3D en7581_pinctrl_funcs, > + .num_funcs =3D ARRAY_SIZE(en7581_pinctrl_funcs), > + .confs_info =3D { > + [AIROHA_PINCTRL_CONFS_PULLUP] =3D { > + .confs =3D en7581_pinctrl_pullup_conf, > + .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pullup_conf), > + }, > + [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { > + .confs =3D en7581_pinctrl_pulldown_conf, > + .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pulldown_conf), > + }, > + [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { > + .confs =3D en7581_pinctrl_drive_e2_conf, > + .num_confs =3D ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), > + }, > + [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { > + .confs =3D en7581_pinctrl_drive_e4_conf, > + .num_confs =3D ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), > + }, > + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] =3D { > + .confs =3D en7581_pinctrl_pcie_rst_od_conf, > + .num_confs =3D ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), > + }, > + }, > +}; > + > +static const struct of_device_id airoha_pinctrl_of_match[] =3D { > + { .compatible =3D "airoha,en7581-pinctrl", .data =3D &en7581_pinctrl_ma= tch_data }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); > + > +static struct platform_driver airoha_pinctrl_driver =3D { > + .probe =3D airoha_pinctrl_probe, > + .driver =3D { > + .name =3D "pinctrl-airoha-an7581", > + .of_match_table =3D airoha_pinctrl_of_match, > + }, > +}; > +module_platform_driver(airoha_pinctrl_driver); > + > +MODULE_LICENSE("GPL"); > +MODULE_AUTHOR("Lorenzo Bianconi "); > +MODULE_AUTHOR("Benjamin Larsson "); > +MODULE_AUTHOR("Markus Gothe "); > +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC"); > diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/ai= roha/pinctrl-an7583.c > new file mode 100644 > index 0000000000000..b9d8dd94de5f0 > --- /dev/null > +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c > @@ -0,0 +1,1456 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Author: Lorenzo Bianconi > + * Author: Benjamin Larsson > + * Author: Markus Gothe > + */ > + > +#include "airoha-common.h" > + > +/* MUX */ > +#define REG_GPIO_2ND_I2C_MODE 0x0214 > +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) > +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) > +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) > +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) > +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) > +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) > +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) > +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) > +#define PON_TOD_1PPS_MODE_MASK BIT(2) > +#define GSW_TOD_1PPS_MODE_MASK BIT(1) > + > +#define REG_GPIO_SPI_CS1_MODE 0x0218 > +#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(22) > +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) > +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) > +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) > +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) > +#define GPIO_PCM_SPI_MODE_MASK BIT(16) > +#define GPIO_PCM2_MODE_MASK BIT(13) > +#define GPIO_PCM1_MODE_MASK BIT(12) > +#define GPIO_PCM_INT_MODE_MASK BIT(9) > +#define GPIO_PCM_RESET_MODE_MASK BIT(8) > +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) > +#define GPIO_SPI_CS4_MODE_MASK BIT(3) > +#define GPIO_SPI_CS3_MODE_MASK BIT(2) > +#define GPIO_SPI_CS2_MODE_MASK BIT(1) > +#define GPIO_SPI_CS1_MODE_MASK BIT(0) > + > +#define REG_GPIO_PON_MODE 0x021c > +#define AN7583_MDIO_0_GPIO_MODE_MASK BIT(26) > +#define AN7583_MDC_0_GPIO_MODE_MASK BIT(25) > +#define AN7583_UART_RXD_GPIO_MODE_MASK BIT(24) > +#define AN7583_UART_TXD_GPIO_MODE_MASK BIT(23) > +#define AN7583_SPI_MISO_GPIO_MODE_MASK BIT(22) > +#define AN7583_SPI_MOSI_GPIO_MODE_MASK BIT(21) > +#define AN7583_SPI_CS_GPIO_MODE_MASK BIT(20) > +#define AN7583_SPI_CLK_GPIO_MODE_MASK BIT(19) > +#define AN7583_I2C1_SDA_GPIO_MODE_MASK BIT(18) > +#define AN7583_I2C1_SCL_GPIO_MODE_MASK BIT(17) > +#define AN7583_I2C0_SDA_GPIO_MODE_MASK BIT(16) > +#define AN7583_I2C0_SCL_GPIO_MODE_MASK BIT(15) > +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) > +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) > +#define SIPO_RCLK_MODE_MASK BIT(11) > +#define GPIO_PCIE_RESET1_MASK BIT(10) > +#define GPIO_PCIE_RESET0_MASK BIT(9) > +#define GPIO_UART5_MODE_MASK BIT(8) > +#define GPIO_UART4_MODE_MASK BIT(7) > +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) > +#define GPIO_HSUART_MODE_MASK BIT(5) > +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) > +#define GPIO_UART2_MODE_MASK BIT(3) > +#define GPIO_SIPO_MODE_MASK BIT(2) > +#define GPIO_EMMC_MODE_MASK BIT(1) > +#define GPIO_PON_MODE_MASK BIT(0) > + > +#define REG_NPU_UART_EN 0x0224 > +#define JTAG_UDI_EN_MASK BIT(4) > +#define JTAG_DFD_EN_MASK BIT(3) > + > +#define REG_FORCE_GPIO_EN 0x0228 > +#define FORCE_GPIO_EN(n) BIT(n) > + > +/* LED MAP */ > +#define REG_LAN_LED0_MAPPING 0x027c > +#define REG_LAN_LED1_MAPPING 0x0280 > + > +#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) > +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (= _n)) > + > +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) > +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (= _n)) > + > +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) > +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (= _n)) > + > +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) > +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (= _n)) > + > +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) > +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (= _n)) > + > +/* CONF */ > +#define REG_I2C_SDA_E2 0x001c > +#define AN7583_I2C1_SCL_E2_MASK BIT(16) > +#define AN7583_I2C1_SDA_E2_MASK BIT(15) > +#define SPI_MISO_E2_MASK BIT(14) > +#define SPI_MOSI_E2_MASK BIT(13) > +#define SPI_CLK_E2_MASK BIT(12) > +#define SPI_CS0_E2_MASK BIT(11) > +#define PCIE1_RESET_E2_MASK BIT(9) > +#define PCIE0_RESET_E2_MASK BIT(8) > +#define AN7583_MDIO_0_E2_MASK BIT(5) > +#define AN7583_MDC_0_E2_MASK BIT(4) > +#define UART1_RXD_E2_MASK BIT(3) > +#define UART1_TXD_E2_MASK BIT(2) > +#define I2C_SCL_E2_MASK BIT(1) > +#define I2C_SDA_E2_MASK BIT(0) > + > +#define REG_I2C_SDA_E4 0x0020 > +#define AN7583_I2C1_SCL_E4_MASK BIT(16) > +#define AN7583_I2C1_SDA_E4_MASK BIT(15) > +#define SPI_MISO_E4_MASK BIT(14) > +#define SPI_MOSI_E4_MASK BIT(13) > +#define SPI_CLK_E4_MASK BIT(12) > +#define SPI_CS0_E4_MASK BIT(11) > +#define PCIE1_RESET_E4_MASK BIT(9) > +#define PCIE0_RESET_E4_MASK BIT(8) > +#define AN7583_MDIO_0_E4_MASK BIT(5) > +#define AN7583_MDC_0_E4_MASK BIT(4) > +#define UART1_RXD_E4_MASK BIT(3) > +#define UART1_TXD_E4_MASK BIT(2) > +#define I2C_SCL_E4_MASK BIT(1) > +#define I2C_SDA_E4_MASK BIT(0) > + > +#define REG_GPIO_L_E2 0x0024 > +#define REG_GPIO_L_E4 0x0028 > +#define REG_GPIO_H_E2 0x002c > +#define REG_GPIO_H_E4 0x0030 > + > +#define REG_I2C_SDA_PU 0x0044 > +#define AN7583_I2C1_SCL_PU_MASK BIT(16) > +#define AN7583_I2C1_SDA_PU_MASK BIT(15) > +#define SPI_MISO_PU_MASK BIT(14) > +#define SPI_MOSI_PU_MASK BIT(13) > +#define SPI_CLK_PU_MASK BIT(12) > +#define SPI_CS0_PU_MASK BIT(11) > +#define PCIE1_RESET_PU_MASK BIT(9) > +#define PCIE0_RESET_PU_MASK BIT(8) > +#define AN7583_MDIO_0_PU_MASK BIT(5) > +#define AN7583_MDC_0_PU_MASK BIT(4) > +#define UART1_RXD_PU_MASK BIT(3) > +#define UART1_TXD_PU_MASK BIT(2) > +#define I2C_SCL_PU_MASK BIT(1) > +#define I2C_SDA_PU_MASK BIT(0) > + > +#define REG_I2C_SDA_PD 0x0048 > +#define AN7583_I2C1_SCL_PD_MASK BIT(16) > +#define AN7583_I2C1_SDA_PD_MASK BIT(15) > +#define SPI_MISO_PD_MASK BIT(14) > +#define SPI_MOSI_PD_MASK BIT(13) > +#define SPI_CLK_PD_MASK BIT(12) > +#define SPI_CS0_PD_MASK BIT(11) > +#define PCIE1_RESET_PD_MASK BIT(9) > +#define PCIE0_RESET_PD_MASK BIT(8) > +#define AN7583_MDIO_0_PD_MASK BIT(5) > +#define AN7583_MDC_0_PD_MASK BIT(4) > +#define UART1_RXD_PD_MASK BIT(3) > +#define UART1_TXD_PD_MASK BIT(2) > +#define I2C_SCL_PD_MASK BIT(1) > +#define I2C_SDA_PD_MASK BIT(0) > + > +#define REG_GPIO_L_PU 0x004c > +#define REG_GPIO_L_PD 0x0050 > +#define REG_GPIO_H_PU 0x0054 > +#define REG_GPIO_H_PD 0x0058 > + > +#define REG_PCIE_RESET_OD 0x018c > +#define PCIE1_RESET_OD_MASK BIT(1) > +#define PCIE0_RESET_OD_MASK BIT(0) > + > +/* PWM MODE CONF */ > +#define REG_GPIO_FLASH_MODE_CFG 0x0034 > +#define GPIO15_FLASH_MODE_CFG BIT(15) > +#define GPIO14_FLASH_MODE_CFG BIT(14) > +#define GPIO13_FLASH_MODE_CFG BIT(13) > +#define GPIO12_FLASH_MODE_CFG BIT(12) > +#define GPIO11_FLASH_MODE_CFG BIT(11) > +#define GPIO10_FLASH_MODE_CFG BIT(10) > +#define GPIO9_FLASH_MODE_CFG BIT(9) > +#define GPIO8_FLASH_MODE_CFG BIT(8) > +#define GPIO7_FLASH_MODE_CFG BIT(7) > +#define GPIO6_FLASH_MODE_CFG BIT(6) > +#define GPIO5_FLASH_MODE_CFG BIT(5) > +#define GPIO4_FLASH_MODE_CFG BIT(4) > +#define GPIO3_FLASH_MODE_CFG BIT(3) > +#define GPIO2_FLASH_MODE_CFG BIT(2) > +#define GPIO1_FLASH_MODE_CFG BIT(1) > +#define GPIO0_FLASH_MODE_CFG BIT(0) > + > +/* PWM MODE CONF EXT */ > +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 > +#define GPIO51_FLASH_MODE_CFG BIT(31) > +#define GPIO50_FLASH_MODE_CFG BIT(30) > +#define GPIO49_FLASH_MODE_CFG BIT(29) > +#define GPIO48_FLASH_MODE_CFG BIT(28) > +#define GPIO47_FLASH_MODE_CFG BIT(27) > +#define GPIO46_FLASH_MODE_CFG BIT(26) > +#define GPIO45_FLASH_MODE_CFG BIT(25) > +#define GPIO44_FLASH_MODE_CFG BIT(24) > +#define GPIO43_FLASH_MODE_CFG BIT(23) > +#define GPIO42_FLASH_MODE_CFG BIT(22) > +#define GPIO41_FLASH_MODE_CFG BIT(21) > +#define GPIO40_FLASH_MODE_CFG BIT(20) > +#define GPIO39_FLASH_MODE_CFG BIT(19) > +#define GPIO38_FLASH_MODE_CFG BIT(18) > +#define GPIO37_FLASH_MODE_CFG BIT(17) > +#define GPIO36_FLASH_MODE_CFG BIT(16) > +#define GPIO31_FLASH_MODE_CFG BIT(15) > +#define GPIO30_FLASH_MODE_CFG BIT(14) > +#define GPIO29_FLASH_MODE_CFG BIT(13) > +#define GPIO28_FLASH_MODE_CFG BIT(12) > +#define GPIO27_FLASH_MODE_CFG BIT(11) > +#define GPIO26_FLASH_MODE_CFG BIT(10) > +#define GPIO25_FLASH_MODE_CFG BIT(9) > +#define GPIO24_FLASH_MODE_CFG BIT(8) > +#define GPIO23_FLASH_MODE_CFG BIT(7) > +#define GPIO22_FLASH_MODE_CFG BIT(6) > +#define GPIO21_FLASH_MODE_CFG BIT(5) > +#define GPIO20_FLASH_MODE_CFG BIT(4) > +#define GPIO19_FLASH_MODE_CFG BIT(3) > +#define GPIO18_FLASH_MODE_CFG BIT(2) > +#define GPIO17_FLASH_MODE_CFG BIT(1) > +#define GPIO16_FLASH_MODE_CFG BIT(0) > + > +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_GPIO_PON_MODE, \ > + (mux_val), \ > + (mux_val) \ > + }, \ > + .regmap_size =3D 1, \ > + } > + > +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_PWM_EXT_MUX, \ > + REG_GPIO_FLASH_MODE_CFG_EXT, \ > + (mux_val), \ > + 0 \ > + }, \ > + .regmap[1] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_GPIO_PON_MODE, \ > + (smux_val), \ > + (smux_val) \ > + }, \ > + .regmap_size =3D 2, \ > + } > + > +/* PWM */ > +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_PWM_MUX, \ > + REG_GPIO_FLASH_MODE_CFG, \ > + (mux_val), \ > + (mux_val) \ > + }, \ > + .regmap_size =3D 1, \ > + } > + > +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_PWM_EXT_MUX, \ > + REG_GPIO_FLASH_MODE_CFG_EXT, \ > + (mux_val), \ > + (mux_val) \ > + }, \ > + .regmap_size =3D 1, \ > + } > + > +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_PWM_EXT_MUX, \ > + REG_GPIO_FLASH_MODE_CFG_EXT, \ > + (mux_val), \ > + (mux_val) \ > + }, \ > + .regmap[1] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_GPIO_PON_MODE, \ > + (smux_val), \ > + (smux_val) \ > + }, \ > + .regmap_size =3D 2, \ > + } > + > +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_GPIO_2ND_I2C_MODE, \ > + (mux_val), \ > + (mux_val), \ > + }, \ > + .regmap[1] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_LAN_LED0_MAPPING, \ > + (map_mask), \ > + (map_val), \ > + }, \ > + .regmap_size =3D 2, \ > + } > + > +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ > + { \ > + .name =3D (gpio), \ > + .regmap[0] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_GPIO_2ND_I2C_MODE, \ > + (mux_val), \ > + (mux_val), \ > + }, \ > + .regmap[1] =3D { \ > + AIROHA_FUNC_MUX, \ > + REG_LAN_LED1_MAPPING, \ > + (map_mask), \ > + (map_val), \ > + }, \ > + .regmap_size =3D 2, \ > + } > + > +static struct pinctrl_pin_desc an7583_pinctrl_pins[] =3D { > + PINCTRL_PIN(2, "gpio0"), > + PINCTRL_PIN(3, "gpio1"), > + PINCTRL_PIN(4, "gpio2"), > + PINCTRL_PIN(5, "gpio3"), > + PINCTRL_PIN(6, "gpio4"), > + PINCTRL_PIN(7, "gpio5"), > + PINCTRL_PIN(8, "gpio6"), > + PINCTRL_PIN(9, "gpio7"), > + PINCTRL_PIN(10, "gpio8"), > + PINCTRL_PIN(11, "gpio9"), > + PINCTRL_PIN(12, "gpio10"), > + PINCTRL_PIN(13, "gpio11"), > + PINCTRL_PIN(14, "gpio12"), > + PINCTRL_PIN(15, "gpio13"), > + PINCTRL_PIN(16, "gpio14"), > + PINCTRL_PIN(17, "gpio15"), > + PINCTRL_PIN(18, "gpio16"), > + PINCTRL_PIN(19, "gpio17"), > + PINCTRL_PIN(20, "gpio18"), > + PINCTRL_PIN(21, "gpio19"), > + PINCTRL_PIN(22, "gpio20"), > + PINCTRL_PIN(23, "gpio21"), > + PINCTRL_PIN(24, "gpio22"), > + PINCTRL_PIN(25, "gpio23"), > + PINCTRL_PIN(26, "gpio24"), > + PINCTRL_PIN(27, "gpio25"), > + PINCTRL_PIN(28, "gpio26"), > + PINCTRL_PIN(29, "gpio27"), > + PINCTRL_PIN(30, "gpio28"), > + PINCTRL_PIN(31, "gpio29"), > + PINCTRL_PIN(32, "gpio30"), > + PINCTRL_PIN(33, "gpio31"), > + PINCTRL_PIN(34, "gpio32"), > + PINCTRL_PIN(35, "gpio33"), > + PINCTRL_PIN(36, "gpio34"), > + PINCTRL_PIN(37, "gpio35"), > + PINCTRL_PIN(38, "gpio36"), > + PINCTRL_PIN(39, "gpio37"), > + PINCTRL_PIN(40, "gpio38"), > + PINCTRL_PIN(41, "i2c0_scl"), > + PINCTRL_PIN(42, "i2c0_sda"), > + PINCTRL_PIN(43, "i2c1_scl"), > + PINCTRL_PIN(44, "i2c1_sda"), > + PINCTRL_PIN(45, "spi_clk"), > + PINCTRL_PIN(46, "spi_cs"), > + PINCTRL_PIN(47, "spi_mosi"), > + PINCTRL_PIN(48, "spi_miso"), > + PINCTRL_PIN(49, "uart_txd"), > + PINCTRL_PIN(50, "uart_rxd"), > + PINCTRL_PIN(51, "pcie_reset0"), > + PINCTRL_PIN(52, "pcie_reset1"), > + PINCTRL_PIN(53, "mdc_0"), > + PINCTRL_PIN(54, "mdio_0"), > +}; > + > +static const int an7583_pon_pins[] =3D { 15, 16, 17, 18, 19, 20 }; > +static const int an7583_pon_tod_1pps_pins[] =3D { 32 }; > +static const int an7583_gsw_tod_1pps_pins[] =3D { 32 }; > +static const int an7583_sipo_pins[] =3D { 34, 35 }; > +static const int an7583_sipo_rclk_pins[] =3D { 34, 35, 33 }; > +static const int an7583_mdio_pins[] =3D { 43, 44 }; > +static const int an7583_uart2_pins[] =3D { 34, 35 }; > +static const int an7583_uart2_cts_rts_pins[] =3D { 32, 33 }; > +static const int an7583_hsuart_pins[] =3D { 30, 31 }; > +static const int an7583_hsuart_cts_rts_pins[] =3D { 28, 29 }; > +static const int an7583_npu_uart_pins[] =3D { 7, 8 }; > +static const int an7583_uart4_pins[] =3D { 7, 8 }; > +static const int an7583_uart5_pins[] =3D { 23, 24 }; > +static const int an7583_i2c0_pins[] =3D { 41, 42 }; > +static const int an7583_i2c1_pins[] =3D { 43, 44 }; > +static const int an7583_jtag_udi_pins[] =3D { 23, 24, 22, 25, 26 }; > +static const int an7583_jtag_dfd_pins[] =3D { 23, 24, 22, 25, 26 }; > +static const int an7583_pcm1_pins[] =3D { 10, 11, 12, 13, 14 }; > +static const int an7583_pcm2_pins[] =3D { 28, 29, 30, 31, 24 }; > +static const int an7583_spi_pins[] =3D { 28, 29, 30, 31 }; > +static const int an7583_spi_quad_pins[] =3D { 25, 26 }; > +static const int an7583_spi_cs1_pins[] =3D { 27 }; > +static const int an7583_pcm_spi_pins[] =3D { 28, 29, 30, 31, 10, 11, 12,= 13 }; > +static const int an7583_pcm_spi_rst_pins[] =3D { 14 }; > +static const int an7583_pcm_spi_cs1_pins[] =3D { 24 }; > +static const int an7583_emmc_pins[] =3D { > + 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 > +}; > +static const int an7583_pnand_pins[] =3D { > + 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 > +}; > +static const int an7583_gpio0_pins[] =3D { 2 }; > +static const int an7583_gpio1_pins[] =3D { 3 }; > +static const int an7583_gpio2_pins[] =3D { 4 }; > +static const int an7583_gpio3_pins[] =3D { 5 }; > +static const int an7583_gpio4_pins[] =3D { 6 }; > +static const int an7583_gpio5_pins[] =3D { 7 }; > +static const int an7583_gpio6_pins[] =3D { 8 }; > +static const int an7583_gpio7_pins[] =3D { 9 }; > +static const int an7583_gpio8_pins[] =3D { 10 }; > +static const int an7583_gpio9_pins[] =3D { 11 }; > +static const int an7583_gpio10_pins[] =3D { 12 }; > +static const int an7583_gpio11_pins[] =3D { 13 }; > +static const int an7583_gpio12_pins[] =3D { 14 }; > +static const int an7583_gpio13_pins[] =3D { 15 }; > +static const int an7583_gpio14_pins[] =3D { 16 }; > +static const int an7583_gpio15_pins[] =3D { 17 }; > +static const int an7583_gpio16_pins[] =3D { 18 }; > +static const int an7583_gpio17_pins[] =3D { 19 }; > +static const int an7583_gpio18_pins[] =3D { 20 }; > +static const int an7583_gpio19_pins[] =3D { 21 }; > +static const int an7583_gpio20_pins[] =3D { 22 }; > +static const int an7583_gpio21_pins[] =3D { 23 }; > +static const int an7583_gpio22_pins[] =3D { 24 }; > +static const int an7583_gpio23_pins[] =3D { 25 }; > +static const int an7583_gpio24_pins[] =3D { 26 }; > +static const int an7583_gpio25_pins[] =3D { 27 }; > +static const int an7583_gpio26_pins[] =3D { 28 }; > +static const int an7583_gpio27_pins[] =3D { 29 }; > +static const int an7583_gpio28_pins[] =3D { 30 }; > +static const int an7583_gpio29_pins[] =3D { 31 }; > +static const int an7583_gpio30_pins[] =3D { 32 }; > +static const int an7583_gpio31_pins[] =3D { 33 }; > +static const int an7583_gpio32_pins[] =3D { 34 }; > +static const int an7583_gpio33_pins[] =3D { 35 }; > +static const int an7583_gpio34_pins[] =3D { 36 }; > +static const int an7583_gpio35_pins[] =3D { 37 }; > +static const int an7583_gpio36_pins[] =3D { 38 }; > +static const int an7583_gpio37_pins[] =3D { 39 }; > +static const int an7583_gpio38_pins[] =3D { 40 }; > +static const int an7583_gpio39_pins[] =3D { 41 }; > +static const int an7583_gpio40_pins[] =3D { 42 }; > +static const int an7583_gpio41_pins[] =3D { 43 }; > +static const int an7583_gpio42_pins[] =3D { 44 }; > +static const int an7583_gpio43_pins[] =3D { 45 }; > +static const int an7583_gpio44_pins[] =3D { 46 }; > +static const int an7583_gpio45_pins[] =3D { 47 }; > +static const int an7583_gpio46_pins[] =3D { 48 }; > +static const int an7583_gpio47_pins[] =3D { 49 }; > +static const int an7583_gpio48_pins[] =3D { 50 }; > +static const int an7583_gpio49_pins[] =3D { 51 }; > +static const int an7583_gpio50_pins[] =3D { 52 }; > +static const int an7583_gpio51_pins[] =3D { 53 }; > +static const int an7583_gpio52_pins[] =3D { 54 }; > +static const int an7583_pcie_reset0_pins[] =3D { 51 }; > +static const int an7583_pcie_reset1_pins[] =3D { 52 }; > + > +static const struct pingroup an7583_pinctrl_groups[] =3D { > + PINCTRL_PIN_GROUP("pon", an7583_pon), > + PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), > + PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), > + PINCTRL_PIN_GROUP("sipo", an7583_sipo), > + PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), > + PINCTRL_PIN_GROUP("mdio", an7583_mdio), > + PINCTRL_PIN_GROUP("uart2", an7583_uart2), > + PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), > + PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), > + PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), > + PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), > + PINCTRL_PIN_GROUP("uart4", an7583_uart4), > + PINCTRL_PIN_GROUP("uart5", an7583_uart5), > + PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), > + PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), > + PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), > + PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), > + PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), > + PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), > + PINCTRL_PIN_GROUP("spi", an7583_spi), > + PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), > + PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), > + PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), > + PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), > + PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), > + PINCTRL_PIN_GROUP("emmc", an7583_emmc), > + PINCTRL_PIN_GROUP("pnand", an7583_pnand), > + PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), > + PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), > + PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), > + PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), > + PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), > + PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), > + PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), > + PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), > + PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), > + PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), > + PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), > + PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), > + PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), > + PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), > + PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), > + PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), > + PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), > + PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), > + PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), > + PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), > + PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), > + PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), > + PINCTRL_PIN_GROUP("gpio22", an7583_gpio22), > + PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), > + PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), > + PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), > + PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), > + PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), > + PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), > + PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), > + PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), > + PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), > + PINCTRL_PIN_GROUP("gpio32", an7583_gpio32), > + PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), > + PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), > + PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), > + PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), > + PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), > + PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), > + PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), > + PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), > + PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), > + PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), > + PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), > + PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), > + PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), > + PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), > + PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), > + PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), > + PINCTRL_PIN_GROUP("gpio49", an7583_gpio49), > + PINCTRL_PIN_GROUP("gpio50", an7583_gpio50), > + PINCTRL_PIN_GROUP("gpio51", an7583_gpio51), > + PINCTRL_PIN_GROUP("gpio52", an7583_gpio52), > + PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), > + PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), > +}; > + > +static const char *const pon_groups[] =3D { "pon" }; > +static const char *const tod_1pps_groups[] =3D { > + "pon_tod_1pps", "gsw_tod_1pps" > +}; > +static const char *const sipo_groups[] =3D { "sipo", "sipo_rclk" }; > +static const char *const an7583_mdio_groups[] =3D { "mdio" }; > +static const char *const uart_groups[] =3D { > + "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", > + "uart4", "uart5" > +}; > +static const char *const jtag_groups[] =3D { "jtag_udi", "jtag_dfd" }; > +static const char *const pcm_groups[] =3D { "pcm1", "pcm2" }; > +static const char *const spi_groups[] =3D { "spi_quad", "spi_cs1" }; > +static const char *const an7583_pcm_spi_groups[] =3D { > + "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1" > +}; > +static const char *const emmc_groups[] =3D { "emmc" }; > +static const char *const pnand_groups[] =3D { "pnand" }; > +static const char *const an7583_gpio_groups[] =3D { > + "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", > + "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", > + "gpio49", "gpio50", "gpio51", "gpio52" > +}; > +static const char *const an7583_pcie_reset_groups[] =3D { > + "pcie_reset0", "pcie_reset1" > +}; > +static const char *const an7583_pwm_groups[] =3D { > + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", > + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", > + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", > + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", > + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", > + "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39", > + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", > + "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51" > +}; > +static const char *const an7583_phy1_led0_groups[] =3D { > + "gpio1", "gpio2", "gpio3", "gpio4" > +}; > +static const char *const an7583_phy2_led0_groups[] =3D { > + "gpio1", "gpio2", "gpio3", "gpio4" > +}; > +static const char *const an7583_phy3_led0_groups[] =3D { > + "gpio1", "gpio2", "gpio3", "gpio4" > +}; > +static const char *const an7583_phy4_led0_groups[] =3D { > + "gpio1", "gpio2", "gpio3", "gpio4" > +}; > +static const char *const an7583_phy1_led1_groups[] =3D { > + "gpio8", "gpio9", "gpio10", "gpio11" > +}; > +static const char *const an7583_phy2_led1_groups[] =3D { > + "gpio8", "gpio9", "gpio10", "gpio11" > +}; > +static const char *const an7583_phy3_led1_groups[] =3D { > + "gpio8", "gpio9", "gpio10", "gpio11" > +}; > +static const char *const an7583_phy4_led1_groups[] =3D { > + "gpio8", "gpio9", "gpio10", "gpio11" > +}; > + > +static const struct airoha_pinctrl_func_group pon_func_group[] =3D { > + { > + .name =3D "pon", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_PON_MODE_MASK, > + GPIO_PON_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] =3D { > + { > + .name =3D "pon_tod_1pps", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_2ND_I2C_MODE, > + PON_TOD_1PPS_MODE_MASK, > + PON_TOD_1PPS_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "gsw_tod_1pps", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_2ND_I2C_MODE, > + GSW_TOD_1PPS_MODE_MASK, > + GSW_TOD_1PPS_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group sipo_func_group[] =3D { > + { > + .name =3D "sipo", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, > + GPIO_SIPO_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "sipo_rclk", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, > + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = =3D { > + { > + .name =3D "mdio", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_SGMII_MDIO_MODE_MASK, > + GPIO_SGMII_MDIO_MODE_MASK > + }, > + .regmap[1] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_MDC_IO_MASTER_MODE_MASK, > + GPIO_MDC_IO_MASTER_MODE_MASK > + }, > + .regmap_size =3D 2, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group uart_func_group[] =3D { > + { > + .name =3D "uart2", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_UART2_MODE_MASK, > + GPIO_UART2_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "uart2_cts_rts", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, > + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "hsuart", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, > + GPIO_HSUART_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > + { > + .name =3D "hsuart_cts_rts", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, > + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "uart4", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_UART4_MODE_MASK, > + GPIO_UART4_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "uart5", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_UART5_MODE_MASK, > + GPIO_UART5_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group jtag_func_group[] =3D { > + { > + .name =3D "jtag_udi", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_NPU_UART_EN, > + JTAG_UDI_EN_MASK, > + JTAG_UDI_EN_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "jtag_dfd", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_NPU_UART_EN, > + JTAG_DFD_EN_MASK, > + JTAG_DFD_EN_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group pcm_func_group[] =3D { > + { > + .name =3D "pcm1", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM1_MODE_MASK, > + GPIO_PCM1_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm2", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM2_MODE_MASK, > + GPIO_PCM2_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group spi_func_group[] =3D { > + { > + .name =3D "spi_quad", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_SPI_QUAD_MODE_MASK, > + GPIO_SPI_QUAD_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "spi_cs1", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_SPI_CS1_MODE_MASK, > + GPIO_SPI_CS1_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "spi_cs2", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_SPI_CS2_MODE_MASK, > + GPIO_SPI_CS2_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "spi_cs3", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_SPI_CS3_MODE_MASK, > + GPIO_SPI_CS3_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "spi_cs4", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_SPI_CS4_MODE_MASK, > + GPIO_SPI_CS4_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[= ] =3D { > + { > + .name =3D "pcm_spi", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_SPI_MODE_MASK, > + GPIO_PCM_SPI_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_int", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_INT_MODE_MASK, > + GPIO_PCM_INT_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_rst", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_RESET_MODE_MASK, > + GPIO_PCM_RESET_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_cs1", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_SPI_CS1_MODE_MASK, > + GPIO_PCM_SPI_CS1_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_cs2", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, > + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_cs3", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_SPI_CS3_MODE_MASK, > + GPIO_PCM_SPI_CS3_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcm_spi_cs4", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_SPI_CS1_MODE, > + GPIO_PCM_SPI_CS4_MODE_MASK, > + GPIO_PCM_SPI_CS4_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group emmc_func_group[] =3D { > + { > + .name =3D "emmc", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_EMMC_MODE_MASK, > + GPIO_EMMC_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group pnand_func_group[] =3D { > + { > + .name =3D "pnand", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_PARALLEL_NAND_MODE_MASK, > + GPIO_PARALLEL_NAND_MODE_MASK > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = =3D { > + AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG, > + AN7583_I2C0_SCL_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG, > + AN7583_I2C0_SDA_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG, > + AN7583_I2C1_SCL_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG, > + AN7583_I2C1_SDA_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG, > + AN7583_SPI_CLK_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG, > + AN7583_SPI_CS_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG, > + AN7583_SPI_MOSI_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG, > + AN7583_SPI_MISO_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, > + AN7583_UART_TXD_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, > + AN7583_UART_RXD_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, > + GPIO_PCIE_RESET0_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG, > + GPIO_PCIE_RESET1_MASK), > + AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG, > + AN7583_MDC_0_GPIO_MODE_MASK), > + AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK), > +}; > + > +static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_gro= up[] =3D { > + { > + .name =3D "pcie_reset0", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_PCIE_RESET0_MASK, > + 0 > + }, > + .regmap_size =3D 1, > + }, { > + .name =3D "pcie_reset1", > + .regmap[0] =3D { > + AIROHA_FUNC_MUX, > + REG_GPIO_PON_MODE, > + GPIO_PCIE_RESET1_MASK, > + 0 > + }, > + .regmap_size =3D 1, > + }, > +}; > + > +static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = =3D { > + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG, > + AN7583_I2C0_SCL_GPIO_MODE_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG, > + AN7583_I2C0_SDA_GPIO_MODE_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG, > + AN7583_I2C1_SCL_GPIO_MODE_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG, > + AN7583_I2C1_SDA_GPIO_MODE_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG, > + AN7583_SPI_CLK_GPIO_MODE_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG, > + AN7583_SPI_CS_GPIO_MODE_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG, > + AN7583_SPI_MOSI_GPIO_MODE_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG, > + AN7583_SPI_MISO_GPIO_MODE_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, > + AN7583_UART_TXD_GPIO_MODE_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, > + AN7583_UART_RXD_GPIO_MODE_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, > + GPIO_PCIE_RESET0_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG, > + GPIO_PCIE_RESET1_MASK), > + AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG, > + AN7583_MDC_0_GPIO_MODE_MASK), > +}; > + > +static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_grou= p[] =3D { > + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), > +}; > + > +static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_grou= p[] =3D { > + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), > +}; > + > +static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_grou= p[] =3D { > + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), > +}; > + > +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_grou= p[] =3D { > + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), > +}; > + > +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_grou= p[] =3D { > + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), > + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), > +}; > + > +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_grou= p[] =3D { > + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), > + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), > +}; > + > +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_grou= p[] =3D { > + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), > + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), > +}; > + > +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_grou= p[] =3D { > + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, > + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, > + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, > + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), > + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, > + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), > +}; > + > +static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] =3D { > + PINCTRL_FUNC_DESC("pon", pon), > + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), > + PINCTRL_FUNC_DESC("sipo", sipo), > + PINCTRL_FUNC_DESC("mdio", an7583_mdio), > + PINCTRL_FUNC_DESC("uart", uart), > + PINCTRL_FUNC_DESC("jtag", jtag), > + PINCTRL_FUNC_DESC("pcm", pcm), > + PINCTRL_FUNC_DESC("spi", spi), > + PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), > + PINCTRL_FUNC_DESC("emmc", emmc), > + PINCTRL_FUNC_DESC("pnand", pnand), > + PINCTRL_FUNC_DESC("gpio", an7583_gpio), > + PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), > + PINCTRL_FUNC_DESC("pwm", an7583_pwm), > + PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), > + PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), > + PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), > + PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), > + PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), > + PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), > + PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), > + PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), > +}; > + > +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] =3D= { > + PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), > + PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), > + PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), > + PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), > + PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), > + PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), > + PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), > + PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), > + PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), > + PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), > + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), > + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), > + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), > + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), > + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), > + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), > + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), > + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), > + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), > + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)), > + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), > + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), > + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), > + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), > + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), > + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), > + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), > + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), > + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), > + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), > + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), > + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), > + PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), > + PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), > + PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), > + PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), > + PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), > + PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), > + PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), > + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), > + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), > + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK), > + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK), > + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), > + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), > + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), > + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), > + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), > + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), > + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), > + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), > + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK), > + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), > +}; > + > +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = =3D { > + PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), > + PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), > + PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), > + PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), > + PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), > + PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), > + PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), > + PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), > + PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), > + PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), > + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), > + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), > + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), > + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), > + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), > + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), > + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), > + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), > + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), > + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)), > + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), > + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), > + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), > + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), > + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), > + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), > + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), > + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), > + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), > + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), > + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), > + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), > + PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), > + PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), > + PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), > + PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), > + PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), > + PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), > + PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), > + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), > + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), > + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK), > + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK), > + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), > + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), > + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), > + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), > + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), > + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), > + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), > + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), > + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK), > + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), > +}; > + > +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = =3D { > + PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), > + PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), > + PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), > + PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), > + PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), > + PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), > + PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), > + PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), > + PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), > + PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), > + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), > + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), > + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), > + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), > + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), > + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), > + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), > + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), > + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), > + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)), > + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), > + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), > + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), > + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), > + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), > + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), > + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), > + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), > + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), > + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), > + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), > + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), > + PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), > + PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), > + PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), > + PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), > + PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), > + PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), > + PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), > + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), > + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), > + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK), > + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK), > + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), > + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), > + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), > + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), > + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), > + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), > + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), > + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), > + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK), > + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), > +}; > + > +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = =3D { > + PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), > + PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), > + PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), > + PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), > + PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), > + PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), > + PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), > + PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), > + PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), > + PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), > + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), > + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), > + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), > + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), > + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), > + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), > + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), > + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), > + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), > + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)), > + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), > + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), > + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), > + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), > + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), > + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), > + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), > + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), > + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), > + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), > + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), > + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), > + PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), > + PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), > + PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), > + PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), > + PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), > + PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), > + PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), > + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), > + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), > + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK), > + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK), > + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), > + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), > + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), > + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), > + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), > + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), > + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), > + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), > + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK), > + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), > +}; > + > +static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[= ] =3D { > + PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), > + PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), > +}; > + > +static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = =3D { > + .pinctrl_name =3D KBUILD_MODNAME, > + .pinctrl_owner =3D THIS_MODULE, > + .pins =3D an7583_pinctrl_pins, > + .num_pins =3D ARRAY_SIZE(an7583_pinctrl_pins), > + .grps =3D an7583_pinctrl_groups, > + .num_grps =3D ARRAY_SIZE(an7583_pinctrl_groups), > + .funcs =3D an7583_pinctrl_funcs, > + .num_funcs =3D ARRAY_SIZE(an7583_pinctrl_funcs), > + .confs_info =3D { > + [AIROHA_PINCTRL_CONFS_PULLUP] =3D { > + .confs =3D an7583_pinctrl_pullup_conf, > + .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pullup_conf), > + }, > + [AIROHA_PINCTRL_CONFS_PULLDOWN] =3D { > + .confs =3D an7583_pinctrl_pulldown_conf, > + .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pulldown_conf), > + }, > + [AIROHA_PINCTRL_CONFS_DRIVE_E2] =3D { > + .confs =3D an7583_pinctrl_drive_e2_conf, > + .num_confs =3D ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), > + }, > + [AIROHA_PINCTRL_CONFS_DRIVE_E4] =3D { > + .confs =3D an7583_pinctrl_drive_e4_conf, > + .num_confs =3D ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), > + }, > + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] =3D { > + .confs =3D an7583_pinctrl_pcie_rst_od_conf, > + .num_confs =3D ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf), > + }, > + }, > +}; > + > +static const struct of_device_id airoha_pinctrl_of_match[] =3D { > + { .compatible =3D "airoha,an7583-pinctrl", .data =3D &an7583_pinctrl_ma= tch_data }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); > + > +static struct platform_driver airoha_pinctrl_driver =3D { > + .probe =3D airoha_pinctrl_probe, > + .driver =3D { > + .name =3D "pinctrl-airoha-an7583", > + .of_match_table =3D airoha_pinctrl_of_match, > + }, > +}; > +module_platform_driver(airoha_pinctrl_driver); > + > +MODULE_LICENSE("GPL"); > +MODULE_AUTHOR("Lorenzo Bianconi "); > +MODULE_AUTHOR("Benjamin Larsson "); > +MODULE_AUTHOR("Markus Gothe "); > +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC"); > --=20 > 2.53.0 >=20 --bXde1pkZXIZW6GKB Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTquNwa3Txd3rGGn7Y6cBh0uS2trAUCamchjgAKCRA6cBh0uS2t rLRZAQDfmxC/8o9ELx77S22CbAZf8dY8r5ZJc0jTyFwyDE3t2wEA58xpNrumxU54 Kz47TjW81WIZpuBsNtCbNIAyoZwQ/gY= =tNd/ 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