From: Frank Li <Frank.li@oss.nxp.com>
To: haibo.chen@oss.nxp.com
Cc: Han Xu <han.xu@nxp.com>, Yogesh Gaur <yogeshgaur.83@gmail.com>,
Mark Brown <broonie@kernel.org>,
linux-spi@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, Haibo Chen <haibo.chen@nxp.com>
Subject: Re: [PATCH v2 1/3] spi: spi-nxp-fspi: add per-SoC SDR/DTR clock rate limits for all supported SoCs
Date: Tue, 28 Jul 2026 10:14:44 -0500 [thread overview]
Message-ID: <amjHZH2VdhueF7e0@SMW015318> (raw)
In-Reply-To: <20260728-fspi-clock-v2-1-dbe786a4a6eb@nxp.com>
On Tue, Jul 28, 2026 at 06:18:08PM +0800, haibo.chen@oss.nxp.com wrote:
> From: Haibo Chen <haibo.chen@nxp.com>
>
> The commit f43579ef3500 ("spi: spi-nxp-fspi: limit the clock rate for
> different sample clock source selection") introduced a global 166MHz
> cap for DTR mode (RXCLKSRC=3), based on the i.MX8MN datasheet timing
> specification (Section 3.9.9, page 65).
>
> After reviewing the FlexSPI timing parameters in the datasheets for all
> supported SoCs, the following corrections and additions are needed:
>
> 1. SDR mode (RXCLKSRC=0) limits vary per SoC:
> - i.MX8MN/MM/MP/95: 66MHz (IMX8MNCEC §3.9.9, IMX8MMCEC §3.9.10,
> IMX8MPCEC, IMX95CEC Rev.8 §4.11.7)
> - i.MX8QXP/QM/DXL/ULP: 60MHz (IMX8QXPCEC, IMX8QMCEC, IMX8DXLCEC,
> IMX8ULPCEC §7.3.1 ND mode)
> - LX2160A: 100MHz (LX2160ACEC FlexSPI timing parameters)
>
> 2. DTR mode (RXCLKSRC=3) limits vary per SoC:
> - i.MX8MN/MM/MP/ULP: 166MHz
> - i.MX8QXP/QM/DXL: 200MHz (same FlexSPI IP across this family)
> - i.MX95: 200MHz (IMX95CEC §4.11.7.3.2.3 Table 106)
> - LX2160A: DTR disabled (FSPI_QUIRK_DISABLE_DTR)
>
> Update related platform data with correct speed limation according
> to datasheet.
>
> Fixes: f43579ef3500 ("spi: spi-nxp-fspi: limit the clock rate for different sample clock source selection")
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/spi/spi-nxp-fspi.c | 83 ++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 80 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
> index d94a2a7b98d44db217ba96a8ce7df23e37a08ba4..6de6d432cdcb2ee383a02d72f20000045903e176 100644
> --- a/drivers/spi/spi-nxp-fspi.c
> +++ b/drivers/spi/spi-nxp-fspi.c
> @@ -340,6 +340,18 @@ struct nxp_fspi_devtype_data {
> unsigned int quirks;
> unsigned int lut_num;
> bool little_endian;
> + /*
> + * The max clock rate (Hz) that FlexSPI can output to the device
> + * in SDR mode (RXCLKSRC=0). Defaults to 66MHz if zero.
> + * Some SoCs (e.g. LX2160A) support up to 100MHz in SDR mode.
> + */
> + unsigned long max_sdr_rate;
> + /*
> + * The max clock rate (Hz) that FlexSPI can output to the device
> + * in DTR mode (RXCLKSRC=3). Defaults to 166MHz if zero.
> + * Some SoCs (e.g. i.MX95, i.MX8QM, i.MX8DXL) support up to 200MHz.
> + */
> + unsigned long max_dtr_rate;
> };
>
> static struct nxp_fspi_devtype_data lx2160a_data = {
> @@ -349,6 +361,10 @@ static struct nxp_fspi_devtype_data lx2160a_data = {
> .quirks = FSPI_QUIRK_DISABLE_DTR,
> .lut_num = 32,
> .little_endian = true, /* little-endian */
> + /*
> + * LX2160ACEC: SDR RXCLKSRC=0 max 100MHz, DTR disabled via quirk.
> + */
> + .max_sdr_rate = 100000000,
> };
>
> static struct nxp_fspi_devtype_data imx8mm_data = {
> @@ -358,6 +374,21 @@ static struct nxp_fspi_devtype_data imx8mm_data = {
> .quirks = 0,
> .lut_num = 32,
> .little_endian = true, /* little-endian */
> + /* IMX8MMCEC §3.9.10: SDR RXCLKSRC=0 max 66MHz, DDR RXCLKSRC=3 max 166MHz */
> + .max_sdr_rate = 66000000,
> + .max_dtr_rate = 166000000,
> +};
> +
> +static struct nxp_fspi_devtype_data imx8mp_data = {
> + .rxfifo = SZ_512, /* (64 * 64 bits) */
> + .txfifo = SZ_1K, /* (128 * 64 bits) */
> + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
> + .quirks = 0,
> + .lut_num = 32,
> + .little_endian = true, /* little-endian */
> + /* IMX8MPCEC: SDR RXCLKSRC=0 max 66MHz, DDR RXCLKSRC=3 max 166MHz */
> + .max_sdr_rate = 66000000,
> + .max_dtr_rate = 166000000,
> };
>
> static struct nxp_fspi_devtype_data imx8qxp_data = {
> @@ -367,6 +398,12 @@ static struct nxp_fspi_devtype_data imx8qxp_data = {
> .quirks = 0,
> .lut_num = 32,
> .little_endian = true, /* little-endian */
> + /*
> + * IMX8QXPCEC: SDR RXCLKSRC=0 max 60MHz, DDR RXCLKSRC=3 max 200MHz.
> + * i.MX8QM and i.MX8DXL share the same FlexSPI IP and limits.
> + */
> + .max_sdr_rate = 60000000,
> + .max_dtr_rate = 200000000,
> };
>
> static struct nxp_fspi_devtype_data imx8dxl_data = {
> @@ -376,6 +413,12 @@ static struct nxp_fspi_devtype_data imx8dxl_data = {
> .quirks = FSPI_QUIRK_USE_IP_ONLY,
> .lut_num = 32,
> .little_endian = true, /* little-endian */
> + /*
> + * IMX8DXLCEC (i.MX 8XLite): SDR RXCLKSRC=0 max 60MHz,
> + * DDR RXCLKSRC=3 max 200MHz.
> + */
> + .max_sdr_rate = 60000000,
> + .max_dtr_rate = 200000000,
> };
>
> static struct nxp_fspi_devtype_data imx8ulp_data = {
> @@ -385,6 +428,29 @@ static struct nxp_fspi_devtype_data imx8ulp_data = {
> .quirks = 0,
> .lut_num = 16,
> .little_endian = true, /* little-endian */
> + /*
> + * IMX8ULPCEC §7.3.1, Normal Drive (ND, 1.0V) mode:
> + * SDR RXCLKSRC=0 max 60MHz, DDR RXCLKSRC=3 max 166MHz.
> + * Note: Overdrive (OD, 1.05V) allows up to 180MHz DTR
> + * but is not the default use case.
> + */
> + .max_sdr_rate = 60000000,
> + .max_dtr_rate = 166000000,
> +};
> +
> +static struct nxp_fspi_devtype_data imx95_data = {
> + .rxfifo = SZ_512, /* (64 * 64 bits) */
> + .txfifo = SZ_1K, /* (128 * 64 bits) */
> + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
> + .quirks = 0,
> + .lut_num = 32,
> + .little_endian = true, /* little-endian */
> + /*
> + * IMX95CEC Rev.8 §4.11.7: SDR RXCLKSRC=0 max 66MHz,
> + * DDR RXCLKSRC=3 max 200MHz (Nominal/Overdrive mode).
> + */
> + .max_sdr_rate = 66000000,
> + .max_dtr_rate = 200000000,
> };
>
> struct nxp_fspi {
> @@ -691,10 +757,20 @@ static void nxp_fspi_select_rx_sample_clk_source(struct nxp_fspi *f,
> reg = fspi_readl(f, f->iobase + FSPI_MCR0);
> if (op_is_dtr) {
> reg |= FSPI_MCR0_RXCLKSRC(3);
> - f->max_rate = 166000000;
> + /*
> + * Use the SoC-specific DTR max rate if provided, otherwise
> + * fall back to 166MHz (limit from IMX8MN datasheet §3.9.9).
> + */
> + f->max_rate = f->devtype_data->max_dtr_rate ?
> + f->devtype_data->max_dtr_rate : 166000000;
> } else { /*select mode 0 */
> reg &= ~FSPI_MCR0_RXCLKSRC(3);
> - f->max_rate = 66000000;
> + /*
> + * Use the SoC-specific SDR max rate if provided, otherwise
> + * fall back to 66MHz (limit from IMX8MN datasheet §3.9.9).
> + */
> + f->max_rate = f->devtype_data->max_sdr_rate ?
> + f->devtype_data->max_sdr_rate : 66000000;
> }
> fspi_writel(f, reg, f->iobase + FSPI_MCR0);
> }
> @@ -1457,10 +1533,11 @@ static const struct dev_pm_ops nxp_fspi_pm_ops = {
> static const struct of_device_id nxp_fspi_dt_ids[] = {
> { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
> { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, },
> - { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, },
> + { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mp_data, },
> { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, },
> { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, },
> { .compatible = "nxp,imx8ulp-fspi", .data = (void *)&imx8ulp_data, },
> + { .compatible = "nxp,imx95-fspi", .data = (void *)&imx95_data, },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids);
>
> --
> 2.34.1
>
>
next prev parent reply other threads:[~2026-07-28 15:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-28 10:18 [PATCH v2 0/3] Few fix/improvement for spi-nxp-fspi haibo.chen
2026-07-28 10:18 ` [PATCH v2 1/3] spi: spi-nxp-fspi: add per-SoC SDR/DTR clock rate limits for all supported SoCs haibo.chen
2026-07-28 10:23 ` sashiko-bot
2026-07-28 15:14 ` Frank Li [this message]
2026-07-28 10:18 ` [PATCH v2 2/3] spi: spi-nxp-fspi: enter stop mode before reconfiguring MCR0 and DLL haibo.chen
2026-07-28 10:23 ` sashiko-bot
2026-07-28 15:16 ` Frank Li
2026-07-28 10:18 ` [PATCH v2 3/3] spi: spi-nxp-fspi: propagate clock reconfig failures in nxp_fspi_select_mem() haibo.chen
2026-07-28 10:28 ` sashiko-bot
2026-07-28 15:17 ` Frank Li
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