Re: [PATCH v4 2/3] drm/xe/guc_ads: allocate UM queues in VRAM on dGFX

[Matthew Brost <matthew.brost@intel.com>]

On Thu, Jul 30, 2026 at 02:12:42PM +0100, Matthew Auld wrote:
> On 30/07/2026 11:51, Matthew Auld wrote:
> > On 30/07/2026 01:47, Jia Yao wrote:
> > > On dGFX the original ADS BO is explicitly migrated to VRAM by
> > > xe_guc_realloc_post_hwconfig() so that xe_bo_main_addr() returns a
> > > real device-physical address (DPA) rather than an IOMMU IOVA.  A
> > > separate SYSTEM BO for the UM queues would not go through that migration
> > > path, so its IOVA would differ from the physical address on systems
> > > where pages are allocated above 4 GB.  GuC/GAM accesses the UM queue
> > > ring via base_dpa (with_dpa=true on pre-Xe3p), so an incorrect DPA
> > > causes all-zero fault descriptors to be forwarded to the driver.
> > 
> > I feel like I don't fully understand the explanation here. Is the issue
> > not just the contig requirement for base_dpa? We now use attempt a best
> > effort approach for system memory, however for dgpu we can go further
> > and use VRAM to guarantee that requirement. If that is all this is doing
> > then commit message can be simplified with something like:
> > 
> > "To fully guarantee the contig requirement for base_dpa, we can instead
> > just use VRAM for the um queue, on dgpu..."
> 
> Or is the issue that this has to always be in VRAM, since there is no bit to
> say whether the DPA is system vs VRAM, like we do for the GGTT pte? On dgpu,
> assumption is that this is then always VRAM, if using DPA? If so, please
> make that clearer in the commit message.
> 

The register interface to program the page fault queues are DPA / VRAM
on dGPU iirc.

Matt

> > 
> > > 
> > > Use XE_BO_FLAG_VRAM_IF_DGFX() for the UM queue BO so that on dGFX the
> > > BO is allocated directly in VRAM and xe_bo_main_addr() returns the
> > > correct DPA without needing a post-hwconfig migration step.
> > > 
> > > Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > Cc: Matthew Auld <matthew.auld@intel.com>
> > > Cc: stable@vger.kernel.org
> > > Signed-off-by: Jia Yao <jia.yao@intel.com>
> > > ---
> > >   drivers/gpu/drm/xe/xe_guc.c     |  6 ------
> > >   drivers/gpu/drm/xe/xe_guc_ads.c | 11 ++++++-----
> > >   2 files changed, 6 insertions(+), 11 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> > > index 21cf3edef922..4023700ff2a9 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > > @@ -714,12 +714,6 @@ static int xe_guc_realloc_post_hwconfig(struct
> > > xe_guc *guc)
> > >       if (ret)
> > >           return ret;
> > > -    if (guc->ads.um_queue_bo) {
> > > -        ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc-
> > > >ads.um_queue_bo);
> > > -        if (ret)
> > > -            return ret;
> > > -    }
> > > -
> > >       return 0;
> > >   }
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/
> > > xe_guc_ads.c
> > > index 7f371f9c7268..53636333fb45 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> > > @@ -409,11 +409,12 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
> > >           size_t um_size = roundup_pow_of_two(GUC_UM_QUEUE_SIZE *
> > >                               GUC_UM_HW_QUEUE_MAX);
> > > -        bo = xe_managed_bo_create_pin_map(xe, tile, um_size,
> > > -                          XE_BO_FLAG_SYSTEM |
> > > -                          XE_BO_FLAG_GGTT |
> > > -                          XE_BO_FLAG_GGTT_INVALIDATE |
> > > -                          XE_BO_FLAG_PINNED_NORESTORE);
> > > +        u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> > > +                   XE_BO_FLAG_GGTT |
> > > +                   XE_BO_FLAG_GGTT_INVALIDATE |
> > > +                   XE_BO_FLAG_PINNED_NORESTORE;
> > > +
> > > +        bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags);
> > >           if (IS_ERR(bo))
> > >               return PTR_ERR(bo);
> > 
>