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[34.127.87.210]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3931ced4dc0sm5019116a91.10.2026.08.13.15.30.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2026 15:30:49 -0700 (PDT) Date: Thu, 13 Aug 2026 22:30:45 +0000 From: Samiullah Khawaja To: Alex Williamson Cc: kvm , Alex Williamson , Jason Gunthorpe , Bjorn Helgaas , Kevin Tian , linux-kernel , linux-pci Subject: Re: [RFC PATCH 0/5] PCI/vfio-pci: Guard resets against active SR-IOV VFs Message-ID: References: <20260812045325.2733631-1-alex.williamson@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20260812045325.2733631-1-alex.williamson@nvidia.com> On Tue, Aug 11, 2026 at 10:53:18PM -0600, Alex Williamson wrote: >It's recently been found[1] that vfio-pci doesn't restrict resets on PFs >while SR-IOV is enabled. This can not only result in an uncoordinated >disruption of the use of the associated VFs, but the ongoing use of and >access to the VF has the potential to result in machine checks. > >This series proposes that this gap is largely an oversight of >pci_reset_function() to recognize that a PF reset affecting SR-IOV VFs >violates the scope boundary of the pci_reset_function() API. Hi Alex, Thanks for sending out the RFC to fix this issue. I cherry-picked it into my environment to verify that whether it fixes the issue I was experiencing and it does fix it. I will continue to do more testing, but when you send this as a formal v1, you can add: Tested-by: Samiullah Khawaja Reported-by: Samiullah Khawaja Sami