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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?fAAcVQ5526FHxDxqykECnNPDXkZjazHEzeF+eHZoyCN3injQN0KORV1uJV7B?= =?us-ascii?Q?8pJbEeM921o3A54sNNs5qqmTP3QfSg1jBj5ryMSE9rOTBCA1LOD6OmaGNlZW?= =?us-ascii?Q?4oGV+4cq0WdbOGZrxbZI+1FrKyC7b0mKCZyq6zADjiNVeMuB9D0QQX5YvJj0?= =?us-ascii?Q?INKyqQynUk8SFTPmPrvhiuIDCGeQPiKI0o+wPiy1Umkkdu9tUk3QQkZCQZqS?= =?us-ascii?Q?HPGfy5Rkea3cL8D/adz1Svk/C5UOAxPSaaY+m/3VisVf58GltjSq0dYJOivP?= =?us-ascii?Q?6p4goicMbo+1gdy8sB1lr22f5QfPzNNXNznXGIGsTgQZPF3f/T7iRuMy09wr?= =?us-ascii?Q?NMnOImnqnauWUbrYYh4yrSUqimcVhuCzlyCliVCe2ilnXxsEnYNWfjSR5nOG?= =?us-ascii?Q?o8DP+bIwAoFHyajFeK3OhO6vPblvo03imUiPz4QLjrx5mJi1cFWuHx+UQm3i?= =?us-ascii?Q?Vx8tro+CAp4QmI2bEIYAp4Hj6ybO9rWQFKRQvR0RtjpT8l7usGgLBa+0jRBe?= =?us-ascii?Q?YBU+AMcvT3P8J7QhfaF4u9mC3kA9qEyAOL0Uq4QpkAotnElunF1aTTTQRUhT?= =?us-ascii?Q?RVOZMKYyn301zDf8oOw3jXFxrqH9ERLcPugdVLkpYdVYDWPU8xBTEv0+HuaH?= =?us-ascii?Q?YEwRFV51FMagWJ6EqkpiA+HhonLfZESXuWEmgfA9t1aChdU/nEsPRoMAeh05?= =?us-ascii?Q?oo6xH0wtZptk1fG7KYgvbBEua/HxUi1eGus/Hyi33AnnGwQ4bsesB4cC4eP8?= =?us-ascii?Q?eDbanRP1bx1WfJB8T4kO86y2eAzJrDSKtVwsFLPB5paDLS9Itp0sPViQ6QKh?= =?us-ascii?Q?bDvn0wpm+2stxD7i9qPidX6UpUV6cwHM7PcD96L9SecBJQNtuPoAiGOeqDvS?= =?us-ascii?Q?ymaVcgNhCN2mfI7aSqCNL/Z+CduAgcyUD8IPtsD8RSvaZ0Vy4J381S7Jl33U?= =?us-ascii?Q?0kkIXaNZNEsyQaY3ykUGW7ZbN4XqrMSFRjl8Kc/woU/XwrmtDRiNSlQ8ayyr?= =?us-ascii?Q?okFiu7CSftrOMgF9LY73pz9JJumvhedMMbFEXgJYYedSIMYCWCQ4ZB+oc7An?= =?us-ascii?Q?3fqSWosKzWnxT/erLioVTTDG/Fp5mdczYPAKDihRtHc2SBEFRJt9xAYBLVoG?= =?us-ascii?Q?XeciKhn1nzvvMyfva49a9VUbCxn8EvSwvVYfCfG18OPUPmYIh+8anqcaBO0j?= =?us-ascii?Q?qBYr97ESHaIdpk1O5U0cRWn/hpUJpyc5IvsMcErlxZ2Sw5lNPS8OWbuL0+r3?= =?us-ascii?Q?5xrWLsKypkkUm217+eH+rGktclZhoypyxc3o1Y983+SFqQG3XKAs+hKtDglZ?= =?us-ascii?Q?a7dJF6h5Be8734VdjhGdPZmfJRHM6+ciqytA+mLl8EXyMUI2udOaqu+f36Fd?= =?us-ascii?Q?iObLFHHeVWAfiq4tuRG5kVjnrS6lL4yMvQHQdZ8szLbqij+Ri0T3k0ugejX4?= =?us-ascii?Q?pC0FSz7HdcMBNhcQy7v4mPkL65w6kIARBwggPGzrqfgu58nuC8ZTsISGnZ33?= =?us-ascii?Q?XW84YLEoFv4Vwa/ws2V6/0NdDzSuq7b5998aP1Upoam3Esvm48G16nX01KIi?= =?us-ascii?Q?zfAatO6rLqQVl4kwBTh2TYS0v0t0e4+yocQepNog8yV/6CQfTvqoRp8+mNXu?= =?us-ascii?Q?3UxXZD7niFjZwdqifbKn+sJxT2TzR5gNzp0LdWU37O/doGBv9XmxC/zvPjWc?= =?us-ascii?Q?KzNZ+ZiY+IRqqwEPoQGyjzT3ZRjhjETdwZ4kdXGUV8NrdPRD?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: b694fb00-b7ff-4579-49b8-08def1203ed5 X-MS-Exchange-CrossTenant-AuthSource: BL0PR12MB2370.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2026 05:29:54.3785 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: u9CQZqh9RZnMQ2ns4wQ8ybeeURiudOpa8rCOxNMtndSqt+wPItUfnSUH+pOc8eVpZScdlJQSLBS9fYWY334sHQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH8PR12MB9816 On Fri, Jul 31, 2026 at 04:28:27PM +0800, Dave Jiang wrote: > perf_pmu_unregister() frees pmu->dev without clearing the pointer, and > cxl_pmu_probe() registers its devm actions so that teardown runs > perf_pmu_unregister() first, then the hotplug instance removal, then > free_irq(). Nothing before free_irq() masks the interrupt, so the handler > stays live across a window where info->pmu.dev is freed and its dev_dbg() > walks that pointer. > > Unsharing the interrupt does not close that window. cxl_pmu_event_stop() > leaves the counter's overflow status bit set, and only the handler clears > it, so an overflow taken just before teardown is still delivered and still > gets past the "did anything overflow" early-out. It lands in the !event > branch, where the dev_dbg() is. > > Log through info->pmu.parent instead, which is devm-managed and outlives > every teardown action. > > Clear the overflow status before requesting the interrupt too, since the > driver never touched it at probe and a counter left enabled with > INT_ON_OVRFLW by firmware or a previous kernel can raise an interrupt at > any point. > > Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver") > Reported-by: sashiko-bot@kernel.org > Closes: https://sashiko.dev/#/patchset/20260715191454.459673-1-dave@stgolabs.net?part=1 > Assisted-by: Claude:claude-opus-4-8 > Signed-off-by: Dave Jiang > --- > v3: > - Clear CXL_PMU_OVERFLOW_REG at probe, before the handler is armed. A stale > status bit from firmware can cause overflow interrupt. (Robin) > - Ack dropped as the patch grew a hunk. > - Drop the cxl_pmu_offline_cpu() hunk. That dev_err() cannot be reached. > --- > drivers/perf/cxl_pmu.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c > index 37742ce43d9f..3683427fbb7e 100644 > --- a/drivers/perf/cxl_pmu.c > +++ b/drivers/perf/cxl_pmu.c > @@ -806,7 +806,7 @@ static irqreturn_t cxl_pmu_irq(int irq, void *data) > struct perf_event *event = info->hw_events[i]; > > if (!event) { > - dev_dbg(info->pmu.dev, > + dev_dbg(info->pmu.parent, > "overflow but on non enabled counter %d\n", i); > continue; > } > @@ -903,6 +903,15 @@ static int cxl_pmu_probe(struct device *dev) > if (!irq_name) > return -ENOMEM; > > + /* > + * Clear any overflow status left set by firmware or a previous kernel > + * before the handler goes live, so it cannot mistake a stale bit for an > + * overflow on a counter no event owns yet. The register is RW1C, and > + * bits above the implemented counters are RsvdZ, so only write those. > + */ > + writeq(GENMASK_ULL(info->num_counters - 1, 0), > + info->base + CXL_PMU_OVERFLOW_REG); > + Hi Dave, I have a question here, since you are adding a clear, event_start() covers more than probe does. The block is frozen there, and it closes the reuse case as well as the boot one. If a counter's overflow MSI is still in flight when perf reschedule that counter to another event, the handler charges the full period to an event whose prev_count was just zeroed. Also if FW can leave a counter enabled, I'm not sure whether it's possible or not, but if that's the case, is clearing the status bit enough? A leftoever counter with Global Freeze on Overflow but not Interrupt on Overflow will wrap, freeze the whole CPMU, and raise nothing. Best regards, Richard Cheng. > /* > * The handler must run on info->on_cpu, so the interrupt cannot be > * shared - IRQF_NOBALANCING is only honoured for the first action on a > -- > 2.55.0 > >