From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: opensbi@lists.infradead.org, anup.patel@qti.qualcomm.com
Cc: zong.li@sifive.com, greentime.hu@sifive.com, anup@brainfault.org,
scott@riscstar.com, conor@kernel.org, dave.patel@riscstar.com,
raymond.mao@riscstar.com, robin.randhawa@sifive.com,
samuel.holland@sifive.com, pawandeep.oza@oss.qualcomm.com
Subject: Re: [RFC PATCH 02/12] lib: utils: fdt_helper: parse RISC-V Worlds DT properties
Date: Mon, 3 Aug 2026 15:19:55 +0800 [thread overview]
Message-ID: <anBBG9dyACxwHyjr@plin-1878> (raw)
In-Reply-To: <20260626101433.3133466-3-peter.lin@sifive.com>
Hi Anup,
Regarding to the suggestion in your patch:
"[4/5] lib: sbi: Extend hart protection abstraction to allow ID configuration"
https://patchwork.ozlabs.org/comment/3725105/
> The RISC-V world DT property parsing can be done at the
> time of parsing domains from FDT (like already done in this
> series). The hart platform abstraction will be only for configuring
> the RISC-V world CSRs.
I considered moving per-hart pmwid DT properties parsing into
generic_domains_init()->fdt_domains_populate(), but I think
generic_extensions_init()->fdt_parse_worlds_all_harts() is
still the right place for two reasons:
1. riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist are
per-hart properties stored in sbi_hart_features — not
per-domain. They describe the hart's platform-defined WID
configuration, independent of which domain the hart is
assigned to.
2. pmwid parsing should also work on root-domain-only systems
(no /chosen/opensbi-domains in DT). Since
fdt_iterate_each_domain() returns early when the domain
config node is absent, __fdt_parse_domain() is never
called — so placing pmwid parsing there would miss those
hart feature information.
So the flow is:
init_coldboot()
│
├─ sbi_hart_init()
│ └─ hart_detect_features()
│ └─ generic_extensions_init()
│ ├─ fdt_parse_isa_extensions_all_harts() ← /cpus: hf->extensions
│ └─ fdt_parse_worlds_all_harts() ← /cpus: hf->pmwid/pmwidlist/pmlwidlist
│
├─ sbi_domain_finalize()
│ └─ generic_domains_init()
└─ fdt_domains_populate()
├─ traverse /cpus for coldboot hart domain
└─ __fdt_parse_domain() × N
├─ parse wid, wid_deleg ← per-domain S-mode WID
└─ traverse /cpus for hart assignment
Does this reasoning make sense to you? Or did I miss something?
Thanks,
Peter Lin
--
opensbi mailing list
opensbi@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/opensbi
next prev parent reply other threads:[~2026-08-03 7:20 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-26 10:14 [RFC PATCH 00/12] Add RISC-V Worlds ISA support to OpenSBI Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 01/12] lib: sbi_hart: detect RISC-V Worlds ISA extensions Yu-Chien Peter Lin
2026-07-13 20:58 ` Pawandeep Oza
2026-07-20 3:14 ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 02/12] lib: utils: fdt_helper: parse RISC-V Worlds DT properties Yu-Chien Peter Lin
2026-07-09 0:36 ` Pawandeep Oza
2026-07-09 0:42 ` Pawandeep Oza
2026-07-13 21:13 ` Pawandeep Oza
2026-07-20 6:41 ` Yu-Chien Peter Lin
2026-07-20 5:55 ` Yu-Chien Peter Lin
2026-07-20 3:29 ` Yu-Chien Peter Lin
2026-08-03 7:19 ` Yu-Chien Peter Lin [this message]
2026-06-26 10:14 ` [RFC PATCH 03/12] lib: sbi_hart: enforce riscv,pmwid for Worlds ISA Yu-Chien Peter Lin
2026-07-13 21:26 ` Pawandeep Oza
2026-07-20 7:01 ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 04/12] lib: sbi_hart: lock mwid CSR for RoT immutability Yu-Chien Peter Lin
2026-07-13 21:28 ` Pawandeep Oza
2026-07-20 7:36 ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 05/12] include: sbi_domain: add Worlds WID fields Yu-Chien Peter Lin
2026-07-13 21:52 ` Pawandeep Oza
2026-07-20 7:55 ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 06/12] include: sbi_types: add PRIx64 format macro Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 07/12] lib: sbi_domain: print World ID config at boot Yu-Chien Peter Lin
2026-07-13 23:48 ` Pawandeep Oza
2026-07-20 8:24 ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 08/12] lib: sbi_init: print M-mode World ID " Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 09/12] platform: generic: parse root domain WID config from DT Yu-Chien Peter Lin
2026-07-09 0:39 ` Pawandeep Oza
2026-07-20 8:54 ` Yu-Chien Peter Lin
2026-07-20 10:39 ` Anup Patel
2026-07-20 21:14 ` Pawandeep Oza
2026-07-21 6:24 ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 10/12] lib: utils: fdt_domain: parse per-domain WID properties Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 11/12] lib: sbi_domain: add Worlds CSR config on domain entry Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 12/12] docs: add RISC-V Worlds next-wid/next-widlist DT properties Yu-Chien Peter Lin
2026-07-09 0:44 ` [RFC PATCH 00/12] Add RISC-V Worlds ISA support to OpenSBI Pawandeep Oza
2026-07-14 0:33 ` Pawandeep Oza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=anBBG9dyACxwHyjr@plin-1878 \
--to=peter.lin@sifive.com \
--cc=anup.patel@qti.qualcomm.com \
--cc=anup@brainfault.org \
--cc=conor@kernel.org \
--cc=dave.patel@riscstar.com \
--cc=greentime.hu@sifive.com \
--cc=opensbi@lists.infradead.org \
--cc=pawandeep.oza@oss.qualcomm.com \
--cc=raymond.mao@riscstar.com \
--cc=robin.randhawa@sifive.com \
--cc=samuel.holland@sifive.com \
--cc=scott@riscstar.com \
--cc=zong.li@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.