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boundary="===============8718343653234013861==" Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org --===============8718343653234013861== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="c4glmvlaj5ehl2ro" Content-Disposition: inline --c4glmvlaj5ehl2ro Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH] arm64: dts: rockchip: rk3576: add cache hierarchy information to CPU nodes MIME-Version: 1.0 Hi, On Tue, Jul 28, 2026 at 05:46:14PM +0000, Cole Munz wrote: > The RK3576 CPU nodes carry no cache properties, so cache_setup_of_node() > fails with -ENOENT on the first CPU. That error propagates out of > cache_shared_cpu_map_setup(), which discards the topology arm64 had > already derived from CLIDR, and the boot log gets >=20 > cacheinfo: Unable to detect cache hierarchy for CPU 0 >=20 > Add L1 i/d cache size, line-size and sets to all eight CPU nodes, plus > per-cluster unified L2 nodes wired up through next-level-cache. Sizes > come from the RK3576 datasheet: the Cortex-A72 cluster has 48KB L1 I and > 32KB L1 D per core with 1MB of L2, the Cortex-A53 cluster has 32KB L1 I > and 32KB L1 D per core with 512KB of L2. Line size and associativity are > architecturally fixed per the Cortex-A53 and Cortex-A72 TRMs, so the > *-sets values follow as size / (line-size * ways). >=20 > With this applied, lscpu reports the full hierarchy instead of only the > level, type and shared_cpu_list: >=20 > NAME ONE-SIZE ALL-SIZE WAYS TYPE LEVEL SETS PHY-LINE COHERENCY-SI= ZE > L1d 32K 256K 4 Data 1 128 = 64 > L1i 32K 320K 2 Instruction 1 256 = 64 > L2 512K 1.5M 16 Unified 2 512 = 64 >=20 > Tested-by: Alexey Charkov > Signed-off-by: Cole Munz > --- I've checked the numbers against RK3576 TRM and ARM information. Looks all good to me: Reviewed-by: Sebastian Reichel Greetings, -- Sebastian > arch/arm64/boot/dts/rockchip/rk3576.dtsi | 74 ++++++++++++++++++++++++ > 1 file changed, 74 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/d= ts/rockchip/rk3576.dtsi > index e12a2a0cfb89..656513aa999f 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi > @@ -117,6 +117,13 @@ cpu_l0: cpu@0 { > dynamic-power-coefficient =3D <120>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0x8000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <128>; > + next-level-cache =3D <&l2_cache_l>; > }; > =20 > cpu_l1: cpu@1 { > @@ -129,6 +136,13 @@ cpu_l1: cpu@1 { > operating-points-v2 =3D <&cluster0_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0x8000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <128>; > + next-level-cache =3D <&l2_cache_l>; > }; > =20 > cpu_l2: cpu@2 { > @@ -141,6 +155,13 @@ cpu_l2: cpu@2 { > operating-points-v2 =3D <&cluster0_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0x8000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <128>; > + next-level-cache =3D <&l2_cache_l>; > }; > =20 > cpu_l3: cpu@3 { > @@ -153,6 +174,13 @@ cpu_l3: cpu@3 { > operating-points-v2 =3D <&cluster0_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0x8000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <128>; > + next-level-cache =3D <&l2_cache_l>; > }; > =20 > cpu_b0: cpu@100 { > @@ -166,6 +194,13 @@ cpu_b0: cpu@100 { > dynamic-power-coefficient =3D <320>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0xc000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <256>; > + next-level-cache =3D <&l2_cache_b>; > }; > =20 > cpu_b1: cpu@101 { > @@ -178,6 +213,13 @@ cpu_b1: cpu@101 { > operating-points-v2 =3D <&cluster1_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0xc000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <256>; > + next-level-cache =3D <&l2_cache_b>; > }; > =20 > cpu_b2: cpu@102 { > @@ -190,6 +232,13 @@ cpu_b2: cpu@102 { > operating-points-v2 =3D <&cluster1_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0xc000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <256>; > + next-level-cache =3D <&l2_cache_b>; > }; > =20 > cpu_b3: cpu@103 { > @@ -202,6 +251,31 @@ cpu_b3: cpu@103 { > operating-points-v2 =3D <&cluster1_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0xc000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <256>; > + next-level-cache =3D <&l2_cache_b>; > + }; > + > + l2_cache_l: l2-cache-cluster0 { > + compatible =3D "cache"; > + cache-level =3D <2>; > + cache-unified; > + cache-size =3D <0x80000>; > + cache-line-size =3D <64>; > + cache-sets =3D <512>; > + }; > + > + l2_cache_b: l2-cache-cluster1 { > + compatible =3D "cache"; > + cache-level =3D <2>; > + cache-unified; > + cache-size =3D <0x100000>; > + cache-line-size =3D <64>; > + cache-sets =3D <1024>; > }; > =20 > idle-states { > --=20 > 2.55.0 >=20 >=20 --c4glmvlaj5ehl2ro Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmp6/JgACgkQ2O7X88g7 +po1nw/9G+lG+42+fXZrm08LTFL00t1oNw8LoUhYPM+7n6UwbDJfVEN40XawgOz4 PDKyg/DwYSATccqFdg9YbankJU3hzs1WB6WVto0grv4XkGnn85BMsDp5QO7N1eGW zDgMQbFbaSTQrHBYsJFAGASWMJcL3i1rxQIX0F0rmCEDlVqUgbHdmO43OsiwyRdH MVYpIdInKx/xLxpo/z0C5ZMNp5NlfIJ+qYvpJmYOEiFjKzgU6TK+he1+nMM867DH KCi9eg8GQ+wmITjOaWM1Z81Hs8i/Ntte5YODMcHPt9YDBRiE/Ry0hX3E6ThUCIc6 ti8apfBqFT390KhrNCdlRg6PPx7jlHhunBPffpu6cPEWS5cLba8X/zjaab3ugrlD jsobXYRcVOxlvIjfb+RnfLqCC0cqYUSZPkSbTffnye0wpl05sbh1y8eBZNtmksNN L2LObbm8SeDu8YksIdLxnXOAYoLDEhIO3Csj43tU6BKHpDnHVLg7uSSFkeKu2+6c Gv3Nzo1EATkB9ii0aoXrnDkZb8/3Rh+kCV0g2PDtdi5560UbcfwLl3UMYMyfLp8o u29D+J/VTtrzxODN8PY+OufE90jjyWZNXfjEo50YkjZwsvl9/e4c/2bzORP52Bnv c3w1lXhoEgqqtxuE4aEdsC6ORLBz+Oaaf+0BguB7/JsxobjKyYs= =K2VW -----END PGP SIGNATURE----- --c4glmvlaj5ehl2ro-- --===============8718343653234013861== Content-Type: text/plain; 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bh=25yiAMZ/1b9W5h2xLR5CigmM3pn7DC+Zp5Nh2UiqgXM=; b=RW7NwS9MiymfTmzMxABWzWGWaapHmGDM7YfPyLk156EYOmFQAzFondjDAODAZEaw w4Ilh3PBS7e4ZuenkGmpCs8YUP6etoIH471fUXIgHV61HIf89nSiRIUCpZ4zBHp2KWC b5+194SY6uvmaXoZGV7iczHB/IixHDoOPtLERUbs= Received: by mx.zohomail.com with SMTPS id 1786444959879540.8535890370583; Tue, 11 Aug 2026 03:42:39 -0700 (PDT) Received: by venus (Postfix, from userid 1000) id 2B83718025E; Tue, 11 Aug 2026 12:42:36 +0200 (CEST) Date: Tue, 11 Aug 2026 12:42:36 +0200 From: Sebastian Reichel To: Cole Munz Cc: Heiko Stuebner , linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexey Charkov , Alexey Charkov , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: rockchip: rk3576: add cache hierarchy information to CPU nodes Message-ID: References: <8a8f808a4c7b8325bc253add15e51b396a7d62d1.1785260742.git.Munzzyy1@proton.me> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="c4glmvlaj5ehl2ro" Content-Disposition: inline In-Reply-To: <8a8f808a4c7b8325bc253add15e51b396a7d62d1.1785260742.git.Munzzyy1@proton.me> X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.10.1.5.2/286.434.97 X-ZohoMailClient: External --c4glmvlaj5ehl2ro Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH] arm64: dts: rockchip: rk3576: add cache hierarchy information to CPU nodes MIME-Version: 1.0 Hi, On Tue, Jul 28, 2026 at 05:46:14PM +0000, Cole Munz wrote: > The RK3576 CPU nodes carry no cache properties, so cache_setup_of_node() > fails with -ENOENT on the first CPU. That error propagates out of > cache_shared_cpu_map_setup(), which discards the topology arm64 had > already derived from CLIDR, and the boot log gets >=20 > cacheinfo: Unable to detect cache hierarchy for CPU 0 >=20 > Add L1 i/d cache size, line-size and sets to all eight CPU nodes, plus > per-cluster unified L2 nodes wired up through next-level-cache. Sizes > come from the RK3576 datasheet: the Cortex-A72 cluster has 48KB L1 I and > 32KB L1 D per core with 1MB of L2, the Cortex-A53 cluster has 32KB L1 I > and 32KB L1 D per core with 512KB of L2. Line size and associativity are > architecturally fixed per the Cortex-A53 and Cortex-A72 TRMs, so the > *-sets values follow as size / (line-size * ways). >=20 > With this applied, lscpu reports the full hierarchy instead of only the > level, type and shared_cpu_list: >=20 > NAME ONE-SIZE ALL-SIZE WAYS TYPE LEVEL SETS PHY-LINE COHERENCY-SI= ZE > L1d 32K 256K 4 Data 1 128 = 64 > L1i 32K 320K 2 Instruction 1 256 = 64 > L2 512K 1.5M 16 Unified 2 512 = 64 >=20 > Tested-by: Alexey Charkov > Signed-off-by: Cole Munz > --- I've checked the numbers against RK3576 TRM and ARM information. Looks all good to me: Reviewed-by: Sebastian Reichel Greetings, -- Sebastian > arch/arm64/boot/dts/rockchip/rk3576.dtsi | 74 ++++++++++++++++++++++++ > 1 file changed, 74 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/d= ts/rockchip/rk3576.dtsi > index e12a2a0cfb89..656513aa999f 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi > @@ -117,6 +117,13 @@ cpu_l0: cpu@0 { > dynamic-power-coefficient =3D <120>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0x8000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <128>; > + next-level-cache =3D <&l2_cache_l>; > }; > =20 > cpu_l1: cpu@1 { > @@ -129,6 +136,13 @@ cpu_l1: cpu@1 { > operating-points-v2 =3D <&cluster0_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0x8000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <128>; > + next-level-cache =3D <&l2_cache_l>; > }; > =20 > cpu_l2: cpu@2 { > @@ -141,6 +155,13 @@ cpu_l2: cpu@2 { > operating-points-v2 =3D <&cluster0_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0x8000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <128>; > + next-level-cache =3D <&l2_cache_l>; > }; > =20 > cpu_l3: cpu@3 { > @@ -153,6 +174,13 @@ cpu_l3: cpu@3 { > operating-points-v2 =3D <&cluster0_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0x8000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <128>; > + next-level-cache =3D <&l2_cache_l>; > }; > =20 > cpu_b0: cpu@100 { > @@ -166,6 +194,13 @@ cpu_b0: cpu@100 { > dynamic-power-coefficient =3D <320>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0xc000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <256>; > + next-level-cache =3D <&l2_cache_b>; > }; > =20 > cpu_b1: cpu@101 { > @@ -178,6 +213,13 @@ cpu_b1: cpu@101 { > operating-points-v2 =3D <&cluster1_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0xc000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <256>; > + next-level-cache =3D <&l2_cache_b>; > }; > =20 > cpu_b2: cpu@102 { > @@ -190,6 +232,13 @@ cpu_b2: cpu@102 { > operating-points-v2 =3D <&cluster1_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0xc000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <256>; > + next-level-cache =3D <&l2_cache_b>; > }; > =20 > cpu_b3: cpu@103 { > @@ -202,6 +251,31 @@ cpu_b3: cpu@103 { > operating-points-v2 =3D <&cluster1_opp_table>; > cpu-idle-states =3D <&CPU_SLEEP>; > #cooling-cells =3D <2>; > + i-cache-size =3D <0xc000>; > + i-cache-line-size =3D <64>; > + i-cache-sets =3D <256>; > + d-cache-size =3D <0x8000>; > + d-cache-line-size =3D <64>; > + d-cache-sets =3D <256>; > + next-level-cache =3D <&l2_cache_b>; > + }; > + > + l2_cache_l: l2-cache-cluster0 { > + compatible =3D "cache"; > + cache-level =3D <2>; > + cache-unified; > + cache-size =3D <0x80000>; > + cache-line-size =3D <64>; > + cache-sets =3D <512>; > + }; > + > + l2_cache_b: l2-cache-cluster1 { > + compatible =3D "cache"; > + cache-level =3D <2>; > + cache-unified; > + cache-size =3D <0x100000>; > + cache-line-size =3D <64>; > + cache-sets =3D <1024>; > }; > =20 > idle-states { > --=20 > 2.55.0 >=20 >=20 --c4glmvlaj5ehl2ro Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmp6/JgACgkQ2O7X88g7 +po1nw/9G+lG+42+fXZrm08LTFL00t1oNw8LoUhYPM+7n6UwbDJfVEN40XawgOz4 PDKyg/DwYSATccqFdg9YbankJU3hzs1WB6WVto0grv4XkGnn85BMsDp5QO7N1eGW zDgMQbFbaSTQrHBYsJFAGASWMJcL3i1rxQIX0F0rmCEDlVqUgbHdmO43OsiwyRdH MVYpIdInKx/xLxpo/z0C5ZMNp5NlfIJ+qYvpJmYOEiFjKzgU6TK+he1+nMM867DH KCi9eg8GQ+wmITjOaWM1Z81Hs8i/Ntte5YODMcHPt9YDBRiE/Ry0hX3E6ThUCIc6 ti8apfBqFT390KhrNCdlRg6PPx7jlHhunBPffpu6cPEWS5cLba8X/zjaab3ugrlD jsobXYRcVOxlvIjfb+RnfLqCC0cqYUSZPkSbTffnye0wpl05sbh1y8eBZNtmksNN L2LObbm8SeDu8YksIdLxnXOAYoLDEhIO3Csj43tU6BKHpDnHVLg7uSSFkeKu2+6c Gv3Nzo1EATkB9ii0aoXrnDkZb8/3Rh+kCV0g2PDtdi5560UbcfwLl3UMYMyfLp8o u29D+J/VTtrzxODN8PY+OufE90jjyWZNXfjEo50YkjZwsvl9/e4c/2bzORP52Bnv c3w1lXhoEgqqtxuE4aEdsC6ORLBz+Oaaf+0BguB7/JsxobjKyYs= =K2VW -----END PGP SIGNATURE----- --c4glmvlaj5ehl2ro--