From: Max Chou <max.chou@sifive.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, frank.chang@sifive.com, qemu-riscv@nongnu.org
Subject: Re: [PATCH 10/23] target/riscv: Rewrite vext_ldst_us
Date: Wed, 26 Aug 2026 03:00:32 +0800 [thread overview]
Message-ID: <ao3fnC8rHy3Q3iW0@sifive.com> (raw)
In-Reply-To: <20260815194549.1377505-11-richard.henderson@linaro.org>
On 2026-08-15 12:45, Richard Henderson wrote:
> We already computed the page split here, which means we
> were quite ready to call probe_access directly. Do so,
> then use vext_ldst_nf_{host,tlb} to load the elements.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/tcg/vector_helper.c | 92 ++++++++++++++++++++------------
> 1 file changed, 57 insertions(+), 35 deletions(-)
>
> diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c
> index 7f721dc24d..5b03e23fc3 100644
> --- a/target/riscv/tcg/vector_helper.c
> +++ b/target/riscv/tcg/vector_helper.c
> @@ -483,7 +483,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
> vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz,
> uint32_t evl, uintptr_t ra, bool is_load)
> {
> - target_ulong page_split, elems, addr;
> + target_ulong elems, addr, last, last_in_page, page_split;
> uint32_t nf = vext_nf(desc);
> uint32_t vma = vext_vma(desc);
> uint32_t max_elems = vext_max_elems(desc, log2_esz);
> @@ -491,10 +491,12 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
> uint32_t msize = nf * esz;
> int mmu_index = riscv_env_mmu_index(env, false);
> MMUAccessType access_type = is_load ? MMU_DATA_LOAD : MMU_DATA_STORE;
> + uint32_t i = env->vstart;
> + void *host;
>
> VSTART_CHECK_EARLY_EXIT(env, evl);
>
> - addr = base + env->vstart * msize;
> + addr = base + i * msize;
>
> /* Recognize alignment fault before memory protection fault. */
> vext_test_alignment(env, addr, esz, access_type, mmu_index, ra);
> @@ -505,52 +507,72 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
> * by simply calling ldst_tlb.
> */
> if (nf == 1 && (evl << log2_esz) <= 6) {
> - for (uint32_t i = env->vstart; i < evl;
> - env->vstart = ++i, addr += esz) {
> + for (; i < evl; env->vstart = ++i, addr += esz) {
> ldst_tlb(env, adjust_addr(env, addr), i, vd, ra);
> }
> - env->vstart = 0;
> - if (vma) {
> - vext_set_tail_elems_1s(evl, vd, nf, esz, max_elems);
> - }
> - return;
> + goto tail;
> }
> #endif
>
> - /* Calculate the page range of first page */
> - page_split = -(addr | TARGET_PAGE_MASK);
> - /* Get number of elements */
> - elems = page_split / msize;
> - if (unlikely(env->vstart + elems >= evl)) {
> - elems = evl - env->vstart;
> - }
> + /* Calculate the page range of first page. */
> + last = base + evl * msize - 1;
> + last_in_page = addr | ~TARGET_PAGE_MASK;
> + page_split = last_in_page - addr;
> +
> + /* Validate the first page is accessible. */
> + host = probe_access(env, adjust_addr(env, addr),
> + MIN(last, last_in_page) - addr + 1,
> + access_type, mmu_index, ra);
> +
> + /* Get number of complete elements in the first page. */
> + elems = MIN(page_split / msize, evl - i);
>
The page_split may excludes the byte at last_in_page, which the probe
size includes it. That elems will undercount a complete element ending
at the page boundary.
Then the following cross page element and second page probe will
be affected.
Maybe we could fix it by replacing the page_split with something like
probe_size below:
+ target_unlong probe_bytes = MIN(last, last_in_page) - addr + 1;
/* Validate the first page is accessible. */
- host = probe_access(env, adjust_addr(env, addr),
- MIN(last, last_in_page) - addr + 1,
+ host = probe_access(env, adjust_addr(env, addr), probe_bytes,
access_type, mmu_index, ra);
/* Get number of complete elements in the first page. */
- elems = MIN(page_split / msize, evl - i);
+ elems = MIN(probe_bytes / msize, evl - i);
> + /* Cross page element */
> + if (unlikely(page_split % msize)) {
+ if (unlikely(probe_bytes % msize)) {
> + vext_ldst_nf_tlb(env, vd, addr, i++, nf, esz, max_elems, ldst_tlb, ra);
> + if (i == evl) {
> + goto tail;
> + }
> + env->vstart = i;
> + addr += msize;
> + }
> +
> + /* Validate the second page is accessible. */
> + assert(i < evl);
> + elems = evl - i;
> + host = probe_access(env, adjust_addr(env, addr), elems * msize,
+ probe_bytes = last - addr + 1;
+ host = probe_access(env, adjust_addr(env, addr), probe_bytes,
> + access_type, mmu_index, ra);
rnax
next prev parent reply other threads:[~2026-08-25 19:01 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-15 19:45 [PATCH 00/23] target/riscv: Reorg vector load/store Richard Henderson
2026-08-15 19:45 ` [PATCH 01/23] target/riscv: Split out vext_set_nf_elems_1s Richard Henderson
2026-08-15 19:45 ` [PATCH 02/23] target/riscv: Hoist vma check out of vext_set_tail_elems_1s Richard Henderson
2026-08-16 15:25 ` Richard Henderson
2026-08-15 19:45 ` [PATCH 03/23] target/riscv: Split out vext_ldst_nf_tlb Richard Henderson
2026-08-15 19:45 ` [PATCH 04/23] target/riscv: Split out vext_ldst_nf_host Richard Henderson
2026-08-15 19:45 ` [PATCH 05/23] target/riscv: Add evl argument to vext_ldst_elem_fn_host Richard Henderson
2026-08-16 15:55 ` Richard Henderson
2026-08-25 18:30 ` Max Chou
2026-08-15 19:45 ` [PATCH 06/23] target/riscv: Drop is_load parameter from vext_continuous_ldst_tlb Richard Henderson
2026-08-15 19:45 ` [PATCH 07/23] target/riscv: Remove vext_continuous_ldst_tlb Richard Henderson
2026-08-15 19:45 ` [PATCH 08/23] target/riscv: Move misalignment check out of vext_page_ldst_us Richard Henderson
2026-08-15 19:45 ` [PATCH 09/23] target/riscv: Split out vext_page_ldst_us_{host,tlb} Richard Henderson
2026-08-15 19:45 ` [PATCH 10/23] target/riscv: Rewrite vext_ldst_us Richard Henderson
2026-08-25 19:00 ` Max Chou [this message]
2026-08-15 19:45 ` [PATCH 11/23] target/riscv: Rewrite vext_ldff Richard Henderson
2026-08-25 17:58 ` Max Chou
2026-08-25 20:15 ` Richard Henderson
2026-08-26 18:40 ` Max Chou
2026-08-26 21:33 ` Richard Henderson
2026-08-27 12:48 ` Max Chou
2026-08-15 19:45 ` [PATCH 12/23] target/riscv: Split out vext_ldst_us_desc Richard Henderson
2026-08-15 19:45 ` [PATCH 13/23] target/riscv: Use vext_ldst_us in vext_ldst_whole Richard Henderson
2026-08-15 19:45 ` [PATCH 14/23] target/riscv: Mark VSTART_CHECK_EARLY_EXIT unlikely Richard Henderson
2026-08-15 19:45 ` [PATCH 15/23] target/riscv: Remove unused VDATA,WD Richard Henderson
2026-08-15 19:45 ` [PATCH 16/23] target/riscv: Add MEM_IDX, BSWAP, ALIGN to VDATA Richard Henderson
2026-08-15 19:45 ` [PATCH 17/23] target/riscv: Pass MemOpIdx to vext_ldst_us Richard Henderson
2026-08-15 19:45 ` [PATCH 18/23] target/riscv: Build MemOpIdx to vext_ldff Richard Henderson
2026-08-15 19:45 ` [PATCH 19/23] target/riscv: Pass MemOpIdx to vext_ldst_elem_fn_tlb Richard Henderson
2026-08-15 19:45 ` [PATCH 20/23] target/riscv: Use FLATTEN rather than ALWAYS_INLINE for vector ldst Richard Henderson
2026-08-15 19:45 ` [PATCH 21/23] target/riscv: Drop v0 argument from gen_helper_ldst_us Richard Henderson
2026-08-15 19:45 ` [PATCH 22/23] target/riscv: Drop v0 argument from gen_helper_ldst_stride Richard Henderson
2026-08-15 19:45 ` [PATCH 23/23] target/riscv: Drop v0 argument from gen_helper_ldst_index Richard Henderson
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