Re: [PATCH v2 06/11] drm/xe/cper: Log CPER records for aggregate counter retrival

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Tue, Aug 25, 2026 at 11:29:23PM +0530, Badal Nilawar wrote:
> Log CPER records for aggregate counter retrieval from userspace.

please add a better commit message.

> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_ras.c | 92 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 92 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 27c78800b5d2..ff9d917b8e29 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -204,6 +204,34 @@ static inline const char *comp_to_str(u8 component)
>  	return xe_ras_components[component];
>  }
>  
> +static u32 ras_comp_to_hw_sigid(u8 component)
> +{
> +	switch (component) {
> +	case XE_RAS_COMP_DEVICE_MEMORY:
> +		return XE_SIGID_DEVICE_MEMORY;
> +	case XE_RAS_COMP_CORE_COMPUTE:
> +		return XE_SIGID_CORE_COMPUTE;
> +	case XE_RAS_COMP_PCIE:
> +		return XE_SIGID_PCIE;
> +	case XE_RAS_COMP_FABRIC:
> +		return XE_SIGID_FABRIC;
> +	case XE_RAS_COMP_SOC_INTERNAL:
> +		return XE_SIGID_SOC_INTERNAL;
> +	default:
> +		return U32_MAX;
> +	}
> +}
> +
> +static u8 ras_sev_to_cper_sev(u8 ras_sev)
> +{
> +	switch (ras_sev) {
> +	case XE_RAS_SEV_CORRECTABLE:   return CPER_SEV_CORRECTED;     /* 2 */
> +	case XE_RAS_SEV_UNCORRECTABLE: return CPER_SEV_RECOVERABLE;   /* 0 */
> +	case XE_RAS_SEV_INFORMATIONAL: return CPER_SEV_INFORMATIONAL; /* 3 */

if we have to write the numbers themselves we don't need enums and defines.
Please remove these comments....

> +	default:                       return CPER_SEV_RECOVERABLE;
> +	}
> +}
> +
>  static bool ras_counter_is_valid(struct xe_device *xe, struct xe_ras_error_class *counter)
>  {
>  	u8 severity = counter->common.severity;
> @@ -749,6 +777,66 @@ prepare_cper_error_info(struct xe_device *xe,
>  	return einfo_arr;
>  }
>  
> +static void emit_hw_error_cper(struct xe_device *xe,
> +			       struct xe_ras_error_class *error_class,
> +			       struct xe_ras_get_counter_response *resp,
> +			       u32 sig_id, u8 severity)
> +{
> +	struct xe_ras_get_counter_response local_resp = {};
> +	struct xe_ras_get_counter_response *counter_response = resp;
> +	struct xe_cper_sec_intel_err_hdr ihdr = {};
> +	struct xe_cper_einfo_entry *einfo_arr = NULL;
> +	u32 einfo_count = 0;
> +	u32 i;
> +
> +	if (!counter_response) {
> +		counter_response = &local_resp;
> +		if (get_counter(xe, error_class, counter_response)) {
> +			xe_err(xe, "[RAS]: CPER: failed to get counter, skipping record\n");
> +			return;
> +		}
> +	}
> +
> +	if (counter_response->has_info_queue) {
> +		einfo_arr = prepare_cper_error_info(xe, counter_response,
> +						    error_class, &einfo_count);
> +		if (!einfo_arr)
> +			xe_err(xe, "[RAS]: CPER: failed to build einfo from info queue\n");
> +	}
> +
> +	if (einfo_count > 0) {
> +		for (i = 0; i < einfo_count; i++) {
> +			struct xe_cper_sec_intel_err_hdr entry_ihdr = {};
> +
> +			xe_cper_init_intel_err_hdr(xe,
> +						   (const u8 *)&einfo_arr[i].hdr.error_class,
> +						   einfo_arr[i].timestamp,
> +						   sig_id,
> +						   einfo_arr[i].hdr.counter,
> +						   &entry_ihdr);
> +
> +			xe_cper_record_emit(xe, severity, &INTEL_CPER_NOTIFY_GPU_ERROR,
> +					    &entry_ihdr, einfo_arr[i].einfo,
> +					    einfo_arr[i].einfo_size);
> +		}
> +	} else {
> +		xe_cper_init_intel_err_hdr(xe,
> +					   (const u8 *)error_class,
> +					   counter_response->timestamp,
> +					   sig_id,
> +					   counter_response->value,
> +					   &ihdr);
> +		xe_cper_record_emit(xe, severity, &INTEL_CPER_NOTIFY_GPU_ERROR,
> +				    &ihdr, NULL, 0);
> +	}
> +
> +	if (einfo_arr) {
> +		for (i = 0; i < einfo_count; i++)
> +			kfree(einfo_arr[i].einfo);
> +		kfree(einfo_arr);
> +	}
> +}
> +
>  /**
>   * xe_ras_process_errors() - Process and contain hardware errors
>   * @xe: xe device instance
> @@ -886,6 +974,10 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
>  		return ret;
>  
>  	*value = response.value;
> +
> +	emit_hw_error_cper(xe, &counter, &response,
> +			   ras_comp_to_hw_sigid(counter.common.component),
> +			   ras_sev_to_cper_sev(counter.common.severity));
>  	return 0;
>  }
>  
> -- 
> 2.54.0
>