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[85.229.7.191]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c250a88af72sm443921466b.36.2026.08.26.01.29.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 01:29:54 -0700 (PDT) Date: Wed, 26 Aug 2026 10:29:52 +0200 From: Anders Roxell To: Anshul Dalal Cc: u-boot@lists.u-boot-project.org, marek.vasut@mailbox.org, trini@konsulko.com, ilias.apalodimas@linaro.org, michal.simek@amd.com, lukma@denx.de, alchark@flipper.net, jerome.forissier@arm.com, dlechner@baylibre.com, sjg@chromium.org, Chintan Vankar , Siddharth Vadapalli Subject: Re: [PATCH v7 00/24] usb: dwc3: part 2, make the resynced code work Message-ID: References: <20260824154133.217744-1-anders.roxell@linaro.org> <178765097973.1498018.5668901885485543636.b4-review@b4> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <178765097973.1498018.5668901885485543636.b4-review@b4> X-Mailman-Approved-At: Wed, 26 Aug 2026 13:01:55 +0000 X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org On 2026-08-25 15:12, Anshul Dalal wrote: > On Mon, 24 Aug 2026 17:41:09 +0200, Anders Roxell wrote: > > [...] > > dwc2 with and without DM_USB_GADGET, at91_udc, atmel_usba_udc, ci_udc, > > musb-new and mtu3. 17 boards in total. > > > > DFU is tested on hardware on BeagleBoard-X15, and on BeaglePlay by > > Anshul. ci_udc is tested on an i.MX93 board with ums. The rest is build > > tested only. > > Hi Anders, > > Thanks for reworking the series, I was able to get DFU boot to work properly > and the usb devices are being discovered properly too. > > Though I ran into an issue while using ums with your patches as the host isn't > able to detect the connected device. With default logs I only see a > '\dwc3-generic-peripheral usb@31000000: unknown endpoint event 0'. > > Further debug logs are below on TI's AM62p EVM: > > @ => ums mmc 1 > @ UMS: LUN 0, dev mmc 1, hwpart 0, sector 0x0, count 0x3b72400 > @ g_dnl_register: g_dnl_driver.name = usb_dnl_ums > @ g_dnl_bind: gadget: 0x00000000fde7fb68 cdev: 0x00000000fde5cdd0 > @ usb_add_config: adding config #1 'usb_dnload'/00000000fde83cc0 > @ g_dnl_do_config: configuration: 0x00000000fde83cc0 composite dev: 0x00000000fde5cdd0 > @ adding 'Mass Storage Function'/00000000fde5c110 to config 'usb_dnload'/00000000fde83cc0 > @ cfg 1/00000000fde83cc0 speeds: high full > @ usb_add_config: interface 0 = Mass Storage Function/00000000fde5c110 > @ g_dnl_bind: calling usb_gadget_connect for controller 'dwc3-gadget' > @ usb_dnl_ums: ready > @ -dwc3-generic-peripheral usb@31000000: unknown endpoint event 0 > @ |set_config: high speed config #1: usb_dnload > @ \non-core control reqa1.fe v0000 i0000 l1 > > I observed a similar issue on the beagleplay too. Regards! Hi Anshul, I could reproduce it on my BeagleBoard-X15. First I only saw it connect and got happy, so I forgot to look for the disk. It never shows up, and the host gives up after 20 seconds. The resync dropped the cache maintenance in dwc3 gadget.c. The controller reads a stale trb and nothing moves, that is your "unknown endpoint event 0". DFU still worked because it only uses ep0. With the diff below the disk shows up and 64 MiB reads back correctly. It applies on v7. Can you try ums on AM62p and BeaglePlay? Please let me know how it goes before I send the next version. Cheers, Anders diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 028ebd9b9c79..fd0ae9e3e092 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -228,6 +228,10 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, dwc3_gadget_del_and_unmap_request(dep, req, status); req->status = DWC3_REQUEST_STATUS_COMPLETED; + if (req->request.dma && req->request.length) + dwc3_invalidate_cache((uintptr_t)req->request.dma, + req->request.length); + spin_unlock(&dwc->lock); usb_gadget_giveback_request(&dep->endpoint, &req->request); spin_lock(&dwc->lock); @@ -1382,9 +1386,12 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep, * controller to observe the HWO bit set prematurely. * Add a write memory barrier to prevent CPU re-ordering. */ - // FIXME wmb(); + wmb(); trb->ctrl |= DWC3_TRB_CTRL_HWO; + dwc3_flush_cache((uintptr_t)dma, trb_length); + dwc3_flush_cache((uintptr_t)trb, sizeof(*trb)); + dwc3_ep_inc_enq(dep); } @@ -3153,6 +3160,8 @@ static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, { unsigned int count; + dwc3_invalidate_cache((uintptr_t)trb, sizeof(*trb)); + dwc3_ep_inc_deq(dep); req->num_trbs--; @@ -4181,7 +4190,7 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) * Add an explicit write memory barrier to make sure that the update of * clearing DWC3_EVENT_PENDING is observed in dwc3_check_event_buf() */ - // FIXME wmb(); + wmb(); if (dwc->imod_interval) { dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);