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[35.189.192.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499dcad2532sm19052725e9.11.2026.08.26.01.54.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 01:54:23 -0700 (PDT) Date: Wed, 26 Aug 2026 08:54:19 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com, sebastianene@google.com, keirf@google.com Subject: Re: [PATCH v7 23/24] iommu/arm-smmu-v3-kvm: Enable nesting Message-ID: References: <20260715115906.2664882-1-smostafa@google.com> <20260715115906.2664882-24-smostafa@google.com> <178769159057.3356902.13161185498161727294.b4-review@b4> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <178769159057.3356902.13161185498161727294.b4-review@b4> On Tue, Aug 25, 2026 at 05:59:50PM -0300, Jason Gunthorpe wrote: > > [ ... 129 lines skipped ... ] > > + ret = smmu_attach_stage_2(&target); > > + if (ret) > > + return ret; > > + hyp_spin_lock(&smmu->hw_lock); > > + cur_valid = FIELD_GET(STRTAB_STE_0_V, le64_to_cpu(hyp_ste_ptr->data[0])); > > + target_cfg = FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(target.data[0])); > > + target_valid = FIELD_GET(STRTAB_STE_0_V, le64_to_cpu(target.data[0])); > > + if ((cur_valid && !target_valid) || > > + (target_cfg == STRTAB_STE_0_CFG_ABORT)) { > > + WRITE_ONCE(hyp_ste_ptr->data[0], target.data[0]); > > + WARN_ON(smmu_send_cmd(smmu, &cfgi_cmd)); > > + for (i = 1; i < STRTAB_STE_DWORDS; i++) > > + WRITE_ONCE(hyp_ste_ptr->data[i], target.data[i]); > > + } else { > > + for (i = 1; i < STRTAB_STE_DWORDS; i++) > > + WRITE_ONCE(hyp_ste_ptr->data[i], target.data[i]); > > + WARN_ON(smmu_send_cmd(smmu, &cfgi_cmd)); > > + WRITE_ONCE(hyp_ste_ptr->data[0], target.data[0]); > > + } > > This doesn't look good enough, a driver can't safe writely to a valid > STE in any order like this, and it can't make it non-valid or risk > breaking guests. We had this bug in linux already, the hitless STE > update in the hypervisor is mandatory for linux guests using PASID. This piggy-backs on the kernel algorithm, as described in the comment in this patch: + /* + * Summary of each host emulated state vs real HW. + * | Host | HW | + * ============================== + * | V=0 | V=0 | + * | Abort | Abort | + * | Bypass | S2 | + * | S1 | S1+S2 | + * + * For the host, any V=0 transition is not hitless, all other permutations of + * (abort, bypass, S1) transitions are hitless. + * For the HW state, any V=0 transition is not hitless, as all the S2 config is + * always the same (ttbr, vtcr...), all other transitions should be hitless too. + * However, the host is not trusted, which means that any V=0 <=> V=1 transitions + * or any transition to an abort STE we need to enforce writing order of the STE + * dword 0 and add CFGI. + * Otherwise, we write the STE in the opposite order to cover cases from abort + * to S2 or nested. + */ So this way, the hypervisor doesn't break the STE and keeps the host STE transitions hitless. Or there is an example that I missed and is broken by this? Thanks, Mostafa > > You should use the STE programmer logic from the main driver which > gets this right for every scenario a linux guest can trigger. I don't > think there is anything about it that would be difficult for pkvm. > > -- > Jason