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AHgh+Ro3UHKhdeSnG4gUY7pktw2VhrG0J/M7nT22qav2HY3X8CzBlhdlD5dSe8plIWkWr8jW66c=@vger.kernel.org X-Gm-Message-State: AOJu0Yz1jyG8+34ZQlSTjiihWY7yPJye9ga1KFozpuxy4Ch63PeQKyqu 6QudbcHRL5Lw0nV+EzeeMiPO7qj9i4VoJU60IplFNEd3sAEAGWds00/BUbWXtbfeditLdAUkCZK YjGnGAg== X-Received: from pjje11.prod.google.com ([2002:a17:90a:630b:b0:38d:f003:cd24]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:4f:b0:38e:ad9d:1161 with SMTP id 98e67ed59e1d1-3933b833613mr29799421a91.0.1786974389518; Mon, 17 Aug 2026 06:46:29 -0700 (PDT) Date: Mon, 17 Aug 2026 06:46:28 -0700 In-Reply-To: <32c405c0-a05d-49e7-9cc5-3e5918c27df1@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260713105033.15405-1-sarunkod@amd.com> <20260713105033.15405-6-sarunkod@amd.com> <20260713111119.EC35E1F000E9@smtp.kernel.org> <5149127b-32ce-4409-a443-02b5a9600e14@amd.com> <32c405c0-a05d-49e7-9cc5-3e5918c27df1@amd.com> Message-ID: Subject: Re: [RFC PATCH v3 5/6] KVM: SVM: Add support for AMD IOMMU Guest APIC Physical Processor Interrupt (GAPPI) From: Sean Christopherson To: Sairaj Kodilkar Cc: sashiko-reviews@lists.linux.dev, kvm@vger.kernel.org, Vasant Hegde Content-Type: text/plain; charset="us-ascii" On Mon, Aug 17, 2026, Sairaj Kodilkar wrote: > On 8/13/2026 3:29 AM, Sean Christopherson wrote: > > diff --git arch/x86/kvm/svm/avic.c arch/x86/kvm/svm/avic.c > > index c5b1d294b15a..c9a6da646c8e 100644 > > --- arch/x86/kvm/svm/avic.c > > +++ arch/x86/kvm/svm/avic.c > > @@ -1020,6 +1020,9 @@ static void avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, > > > > lockdep_assert_held(&svm->ir_list_lock); > > > > + if (ga_log_intr && gappi && kvm_can_use_device_posted_irqs(vcpu->kvm)) > > + kvm_pi_enable_wakeup_handler(vcpu); > > + > > I am not sure what you mean here, because pi_enable_wakeup_handler does > more than just manipulating the wakeup list, it also updates pi > descriptor which is Intel specific, Sorry, got ahead of myself. I was envisioning a helper that for just the common part, e.g. void kvm_pi_enable_wakeup_handler(struct kvm_vcpu *vcpu) { lockdep_assert_irqs_disabled(); /* * Acquire the wakeup lock using the "sched out" context to workaround * a lockdep false positive. When this is called, schedule() holds * various per-CPU scheduler locks. When the wakeup handler runs, it * holds this CPU's wakeup lock while calling try_to_wake_up(), which * can eventually take the aforementioned scheduler locks, which causes * lockdep to assume there is deadlock. * * Deadlock can't actually occur because IRQs are disabled for the * entirety of the sched_out critical section, i.e. the wakeup handler * can't run while the scheduler locks are held. */ raw_spin_lock_nested(&per_cpu(wakeup_vcpus_on_cpu_lock, vcpu->cpu), PI_LOCK_SCHED_OUT); list_add_tail(&vcpu->pi_wakeup_list, &per_cpu(wakeup_vcpus_on_cpu, vcpu->cpu)); raw_spin_unlock(&per_cpu(wakeup_vcpus_on_cpu_lock, vcpu->cpu)); } > We have following two options: > > Option A: > Adding a new x86_ops > > avic_update_iommu_vcpu_affinity > kvm_pi_enable_wakeup_handler > list handling > kvm_x86_callback(configure_pi) > IOMMU callbacks > > > The new x86_ops makes sure that irte and pi descriptor are configured > correctly. > > Option B: > Common list handling > > The svm and vmx will share function for list handling but IRTE/PI setup > code will remain same. > > avic_update_iommu_vcpu_affinity/pi_enable_wakeup_handler > kvm_add_to_wakeup_list > list handling > IOMMU callbacks Definitely option B.