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X-CSE-ConnectionGUID: SUD+eXS3SjawhwrCmhwtBQ== X-CSE-MsgGUID: j0XTa+aMTaqa0u8iXKu6aw== X-IronPort-AV: E=McAfee;i="6800,10657,11878"; a="113062005" X-IronPort-AV: E=Sophos;i="6.25,230,1779174000"; d="scan'208";a="113062005" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2026 00:01:16 -0700 X-CSE-ConnectionGUID: aTc3McJJS2S2XshxqjC05A== X-CSE-MsgGUID: vDJH+l5eTZeVBDsaD4kygQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,230,1779174000"; d="scan'208";a="260923243" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.245.209]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2026 00:01:13 -0700 Date: Tue, 18 Aug 2026 10:01:11 +0300 From: Andy Shevchenko To: Jonathan Santos Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, michael.hennerich@analog.com, broonie@kernel.org, jonath4nns@gmail.com, marcelo.schmitt1@gmail.com Subject: Re: [PATCH v3 5/6] spi: spi-engine-ex: Add support for multi-CS devices Message-ID: References: <1e369b85711dc01d3494645d8bf60036cdad1134.1786973376.git.Jonathan.Santos@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1e369b85711dc01d3494645d8bf60036cdad1134.1786973376.git.Jonathan.Santos@analog.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Mon, Aug 17, 2026 at 08:33:26PM -0300, Jonathan Santos wrote: > The SPI Engine controller only handled the first chip select when > asserting CS lines and configuring CS polarity inversion, ignoring > additional CS indices present in cs_index_mask. > > Update spi_engine_gen_cs() to iterate over all set bits in > cs_index_mask and toggle each corresponding CS line in the assert mask. > Update spi_engine_setup() likewise so that SPI_CS_HIGH polarity is > applied to every active CS index rather than only index 0. > > Set SPI_CONTROLLER_MULTI_CS in the controller flags to reflect the > capability to the SPI core. ... > + for_each_set_bit(cs_bit, &cs_index_mask, SPI_ENGINE_MAX_CS) > + mask ^= BIT(spi_get_chipselect(spi, cs_bit)); > + for_each_set_bit(cs_bit, &cs_index_mask, SPI_ENGINE_MAX_CS) { > + if (device->mode & SPI_CS_HIGH) > + spi_engine->cs_inv |= BIT(spi_get_chipselect(device, cs_bit)); > + else > + spi_engine->cs_inv &= ~BIT(spi_get_chipselect(device, cs_bit)); > + } Looking at these two I would rather see a helper unsigned long spi_get_chipselect_bits(..., unsigned long index_mask) With that the above becomes for-loop free. mask ^= spi_get_chipselect_bits(spi, cs_index_mask); and if (device->mode & SPI_CS_HIGH) spi_engine->cs_inv |= spi_get_chipselect_bits(device, cs_index_mask)); else spi_engine->cs_inv &= ~spi_get_chipselect_bits(device, cs_index_mask)); respectively. -- With Best Regards, Andy Shevchenko