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Fri, 21 Aug 2026 03:36:48 -0700 (PDT) X-Received: by 2002:a17:90b:394b:b0:381:9028:5945 with SMTP id 98e67ed59e1d1-395c384d95bmr10132085a91.14.1787308608069; Fri, 21 Aug 2026 03:36:48 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-395c467d907sm2662874a91.7.2026.08.21.03.36.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Aug 2026 03:36:47 -0700 (PDT) Date: Fri, 21 Aug 2026 16:06:39 +0530 From: Abhinaba Rakshit To: Konrad Dybcio Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neeraj Soni , Harshal Dev , Kuldeep Singh , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v11 5/6] arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE eMMC nodes Message-ID: References: <20260609-enable-ice-clock-scaling-v11-0-1cebc8b3275b@oss.qualcomm.com> <20260609-enable-ice-clock-scaling-v11-5-1cebc8b3275b@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Authority-Analysis: v=2.4 cv=BcroFLt2 c=1 sm=1 tr=0 ts=6a882a41 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=jk3V8XEzhubCWnqVx50A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: km3i0zzAw2uQTRyndjOwxa7Nd2tCOj6a X-Proofpoint-ORIG-GUID: km3i0zzAw2uQTRyndjOwxa7Nd2tCOj6a X-Proofpoint-Spam-Info: AW1haW4tMjYwODIxMDA3OSBTYWx0ZWRfX1QcG9R68DbdN ySYKHMqOsfy2d/dASFCt6mncwJp7FwL+n9MhAOs8GPn6QW+Zq+pgvQ3/bezNzdkxyxLTjQEan6v ADLz3d7t3scYzglwOTOvI6XK8YcHG+M= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIxMDA3OSBTYWx0ZWRfX8JMp2vh6qtOU NVuZVxPUtrCeym0KIYA1kpWldHz7brYa0/XiDdQ3LQRCQj1O/PKLV/Yem+1+DLXXKoJYqamJ12m uJPnQhP5CVfviirMhe4bFfS0D1g3tLCz8KoiMyzq4Wn81w8HSVZcv/Pa7E5bcoNoNa9cxqYeIZs X5lQQeQ/NDx6n27BleMoJR+ZNVJF5U0OjcV3PZ+qCV3/r9HPy8pSuFMoB6c5auESQSUbXqpcglG EMpFqP5QGrIQxFvevQRPljpGqnjq/TkvSpZ0flaE8dDn1qAmSAVRdg9OLB0Ay/ATolcmls+iGgY GNbw3VDVswXqLw+qo/K/S4Fcrp4cQL4VuzUI0xJWZUJe1q/FsK+UX9HH95CLpJUoh+hWgLxgHZg H5JLIQzkSZu9pZjpRZv2qNLyfiodYvR8ucrnxdhPyvPHfu5MdjUI54ai0t6K+ylgyj/mVvF9zla WKgfEDuAi9dDCobDAmQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-21_03,2026-08-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 phishscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 bulkscore=0 clxscore=1011 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608210079 On Fri, Jun 26, 2026 at 04:28:54PM +0200, Konrad Dybcio wrote: > On 6/22/26 9:38 AM, Abhinaba Rakshit wrote: > > On Thu, Jun 18, 2026 at 03:04:57PM +0200, Konrad Dybcio wrote: > >> On 6/8/26 11:47 PM, Abhinaba Rakshit wrote: > >>> Qualcomm Inline Crypto Engine (ICE) platform driver now, supports > >>> an optional OPP-table. > >>> > >>> Add OPP-table for ICE UFS and ICE eMMC device nodes for Monaco > >>> platform. > >>> > >>> Signed-off-by: Abhinaba Rakshit > >>> --- > >>> arch/arm64/boot/dts/qcom/monaco.dtsi | 37 ++++++++++++++++++++++++++++++++++++ > >>> 1 file changed, 37 insertions(+) > >>> > >>> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi > >>> index a1b6e6211b84d0d5008231c55613a0ccd61b9450..d9298d8b7874b8669b2cded2a28a99dce6eadbda 100644 > >>> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi > >>> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi > >>> @@ -2742,6 +2742,27 @@ ice: crypto@1d88000 { > >>> clock-names = "core", > >>> "iface"; > >>> power-domains = <&gcc GCC_UFS_PHY_GDSC>; > >>> + > >>> + operating-points-v2 = <&ice_opp_table>; > >>> + > >>> + ice_opp_table: opp-table { > >>> + compatible = "operating-points-v2"; > >>> + > >>> + opp-75000000 { > >>> + opp-hz = /bits/ 64 <75000000>; > >>> + required-opps = <&rpmhpd_opp_svs_l1>; > >>> + }; > >>> + > >>> + opp-201600000 { > >>> + opp-hz = /bits/ 64 <201600000>; > >>> + required-opps = <&rpmhpd_opp_svs_l1>; > >>> + }; > >> > >> Since 75 MHz and 201.6 Mhz require the same power level, is the former > >> OPP any useful? > > > > Yes, both use the same power requirements. However recommended by the ICE team, > > the DT should include all opp/freq supported by the hardware. > > Is there any reason at all where the OS would prefer the lower OPP? > > I think you at one point mentioned some dependency vs the storage > controller's clock frequency > Monaco UFS controller supports a 75 MHz clock rate at the same power level, as specified in the hardware description. Although both frequencies (75 and 201.6MHz) use the same power domain (OPP), retaining the 75 MHz ICE OPP allows the ICE clock to align with the UFS controller’s clock frequency. This synchronization is required for the controller’s supported operating modes and can help avoid unnecessary frequency mismatches. Abhinaba Rakshit