Re: [PATCH v3 10/13] arm64: dts: renesas: r9a08g046: Add DU and DSI nodes

[Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>]

Hi Biju,
Thanks for your patch.

On Wed, Aug 26, 2026 at 06:48:44PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add DU and DSI nodes to RZ/G3L SoC DTSI.
> 

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Kind regards,
Tommaso

> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * Dropped renesas,sysc-pwrrdy from dsi node.
> ---
>  arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 77 ++++++++++++++++++++++
>  1 file changed, 77 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index 6ff145dc81fa..cc8bfb24da87 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -696,6 +696,49 @@ ssi3: ssi@100e4c00 {
>  			status = "disabled";
>  		};
>  
> +		dsi: dsi@10850000 {
> +			compatible = "renesas,r9a08g046-mipi-dsi";
> +			reg = <0 0x10850000 0 0x20000>;
> +			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "seq0", "seq1", "vin1", "rcv",
> +					  "ferr", "ppi", "debug";
> +			clocks = <&cpg CPG_CORE R9A08G046_MIPI_DSI_PLLCLK>,
> +				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_SYSCLK>,
> +				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_ACLK>,
> +				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
> +				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_VCLK>,
> +				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_LPCLK>;
> +			clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
> +			resets = <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
> +				 <&cpg R9A08G046_MIPI_DSI_ARESET_N>,
> +				 <&cpg R9A08G046_MIPI_DSI_PRESET_N>;
> +			reset-names = "rst", "arst", "prst";
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					dsi_in: endpoint {
> +						remote-endpoint = <&du_out_dsi>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +				};
> +			};
> +		};
> +
>  		vspd: vsp@10870000 {
>  			compatible = "renesas,r9a08g046-vsp2",
>  				     "renesas,r9a07g044-vsp2";
> @@ -721,6 +764,40 @@ fcpvd: fcp@10880000 {
>  			power-domains = <&cpg>;
>  		};
>  
> +		du: display@10890000 {
> +			compatible = "renesas,r9a08g046-du";
> +			reg = <0 0x10890000 0 0x10000>;
> +			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>,
> +				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>,
> +				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>;
> +			clock-names = "aclk", "pclk", "vclk";
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A08G046_LCDC_RESET_N>;
> +			renesas,vsps = <&vspd 0>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					du_out_dsi: endpoint {
> +						remote-endpoint = <&dsi_in>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +				};
> +
> +				port@2 {
> +					reg = <2>;
> +				};
> +			};
> +		};
> +
>  		gpu: gpu@108b0000 {
>  			compatible = "renesas,r9a08g046-mali",
>  				     "arm,mali-bifrost";
> -- 
> 2.43.0
>