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envelope-from=chao.liu@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Chao Liu From: Chao Liu via Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Thu, Aug 27, 2026 at 07:25:54PM +0800, Daniel Henrique Barboza wrote: > Given that the helpers are public API we should prefix them with > "riscv_" to avoid conflicts when linking with different targets in the > future, i.e. we should not use generic names like > "create_fdt_socket_memory". > > Despite the amount of lines this is a mechanical change and no real > FDT changes are intended. > > Suggested-by: Philippe Mathieu-Daudé > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Thanks, Chao > --- > hw/riscv/fdt-common.c | 45 ++++++++++++++++---------------- > hw/riscv/sifive_u.c | 34 +++++++++++++------------ > hw/riscv/spike.c | 30 ++++++++++++---------- > hw/riscv/tt_atlantis.c | 22 ++++++++-------- > hw/riscv/virt.c | 42 +++++++++++++++--------------- > include/hw/riscv/fdt-common.h | 48 ++++++++++++++++++----------------- > 6 files changed, 117 insertions(+), 104 deletions(-) > > diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c > index aa143a618b..3a8da03cfb 100644 > --- a/hw/riscv/fdt-common.c > +++ b/hw/riscv/fdt-common.c > @@ -14,8 +14,8 @@ > #include "hw/riscv/fdt-common.h" > #include "target/riscv/cpu_bits.h" > > -void *create_board_device_tree(const char *model, const char *compatible, > - int *fdt_size) > +void *riscv_create_board_device_tree(const char *model, const char *compatible, > + int *fdt_size) > { > void *fdt = create_device_tree(fdt_size); > > @@ -38,8 +38,8 @@ void *create_board_device_tree(const char *model, const char *compatible, > return fdt; > } > > -void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, > - int socket_id, bool numa_enabled) > +void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, > + int socket_id, bool numa_enabled) > { > g_autofree char *mem_name = g_strdup_printf("/memory@%"HWADDR_PRIx, addr); > > @@ -52,9 +52,9 @@ void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, > } > } > > -void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, > - int socket_id, uint32_t *intc_phandles, > - int num_harts, bool numa_enabled) > +void riscv_create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, > + int socket_id, uint32_t *intc_phandles, > + int num_harts, bool numa_enabled) > { > g_autofree uint32_t *clint_cells = g_new0(uint32_t, num_harts * 4); > g_autofree char *clint_name = NULL; > @@ -84,7 +84,8 @@ void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, > } > } > > -void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency) > +void riscv_fdt_create_cpu_socket_subnode(void *fdt, > + uint64_t timebase_frequency) > { > qemu_fdt_add_subnode(fdt, "/cpus"); > qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", > @@ -169,11 +170,11 @@ create_fdt_socket_cpu_internal(void *fdt, char *clust_name, RISCVCPU *cpu_ptr, > qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); > } > > -void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, > - int socket_id, int num_harts_socket, > - int socket_hartid_base, uint32_t *phandle, > - uint32_t *intc_phandles, bool numa_enabled, > - bool is_32_bit) > +void riscv_create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, > + int socket_id, int num_harts_socket, > + int socket_hartid_base, uint32_t *phandle, > + uint32_t *intc_phandles, bool numa_enabled, > + bool is_32_bit) > { > g_autofree char *clust_name = NULL; > > @@ -191,21 +192,21 @@ void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, > } > > void > -create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, > - int cpu_id, int socket_id, > - int socket_hartid_base, uint32_t *phandle, > - uint32_t *intc_phandles) > +riscv_create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, > + int cpu_id, int socket_id, > + int socket_hartid_base, uint32_t *phandle, > + uint32_t *intc_phandles) > { > create_fdt_socket_cpu_internal(fdt, clust_name, NULL, cpu_id, > socket_id, socket_hartid_base, > phandle, intc_phandles, false, false); > } > > -void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, > - uint32_t plic_phandle, uint32_t int_cells, > - uint32_t addr_cells, uint32_t *plic_cells, > - uint32_t cells_size, uint32_t ndev_sources, > - bool numa_enabled, int socket_id) > +void riscv_create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, > + uint32_t plic_phandle, uint32_t int_cells, > + uint32_t addr_cells, uint32_t *plic_cells, > + uint32_t cells_size, uint32_t ndev_sources, > + bool numa_enabled, int socket_id) > { > g_autofree char *nodename = NULL; > static const char * const plic_compat[2] = { > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 57a57c96e1..852c48c056 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -108,8 +108,10 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > g_autofree uint32_t *intc_phandles = g_new0(uint32_t, ms->smp.cpus); > g_autofree char *clust_name = NULL; > > - fdt = ms->fdt = create_board_device_tree("SiFive HiFive Unleashed A00", > - "sifive,hifive-unleashed-a00", &s->fdt_size); > + fdt = ms->fdt = riscv_create_board_device_tree( > + "SiFive HiFive Unleashed A00", > + "sifive,hifive-unleashed-a00", > + &s->fdt_size); > > hfclk_phandle = phandle++; > nodename = g_strdup_printf("/hfclk"); > @@ -133,10 +135,10 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); > g_free(nodename); > > - create_fdt_socket_memory(fdt, memmap[SIFIVE_U_DEV_DRAM].base, > - ms->ram_size, 0, false); > + riscv_create_fdt_socket_memory(fdt, memmap[SIFIVE_U_DEV_DRAM].base, > + ms->ram_size, 0, false); > > - fdt_create_cpu_socket_subnode(fdt, CLINT_TIMEBASE_FREQ); > + riscv_fdt_create_cpu_socket_subnode(fdt, CLINT_TIMEBASE_FREQ); > > clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", 0); > qemu_fdt_add_subnode(fdt, clust_name); > @@ -157,15 +159,15 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename); > } > > - create_fdt_socket_cpu_sifive(fdt, clust_name, cpu, 0, 0, > - &phandle, intc_phandles); > + riscv_create_fdt_socket_cpu_sifive(fdt, clust_name, cpu, 0, 0, > + &phandle, intc_phandles); > > g_free(nodename); > } > > - create_fdt_socket_clint(fdt, memmap[SIFIVE_U_DEV_CLINT].base, > - memmap[SIFIVE_U_DEV_CLINT].size, 0, > - intc_phandles, ms->smp.cpus, false); > + riscv_create_fdt_socket_clint(fdt, memmap[SIFIVE_U_DEV_CLINT].base, > + memmap[SIFIVE_U_DEV_CLINT].size, 0, > + intc_phandles, ms->smp.cpus, false); > > nodename = g_strdup_printf("/soc/otp@%lx", > (long)memmap[SIFIVE_U_DEV_OTP].base); > @@ -209,12 +211,12 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > } > } > > - create_fdt_plic(fdt, memmap[SIFIVE_U_DEV_PLIC].base, > - memmap[SIFIVE_U_DEV_PLIC].size, > - plic_phandle, SIFIVE_U_PLIC_INT_CELLS, > - SIFIVE_U_PLIC_ADDR_CELLS, cells, > - cells_length * sizeof(uint32_t), > - SIFIVE_U_PLIC_NUM_SOURCES - 1, false, 0); > + riscv_create_fdt_plic(fdt, memmap[SIFIVE_U_DEV_PLIC].base, > + memmap[SIFIVE_U_DEV_PLIC].size, > + plic_phandle, SIFIVE_U_PLIC_INT_CELLS, > + SIFIVE_U_PLIC_ADDR_CELLS, cells, > + cells_length * sizeof(uint32_t), > + SIFIVE_U_PLIC_NUM_SOURCES - 1, false, 0); > g_free(cells); > > gpio_phandle = phandle++; > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 630b65f569..8d7e93807c 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -61,8 +61,10 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > uint32_t phandle = 1; > bool numa_enabled = riscv_numa_enabled(ms); > > - fdt = ms->fdt = create_board_device_tree("ucbbar,spike-bare,qemu", > - "ucbbar,spike-bare-dev", &fdt_size); > + fdt = ms->fdt = riscv_create_board_device_tree( > + "ucbbar,spike-bare,qemu", > + "ucbbar,spike-bare-dev", > + &fdt_size); > > qemu_fdt_add_subnode(fdt, "/htif"); > qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); > @@ -71,7 +73,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); > } > > - fdt_create_cpu_socket_subnode(fdt, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); > + riscv_fdt_create_cpu_socket_subnode(fdt, > + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); > > for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) { > g_autofree uint32_t *intc_phandles = g_new0(uint32_t, > @@ -80,20 +83,21 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > riscv_socket_mem_offset(ms, socket); > uint64_t memsize = riscv_socket_mem_size(ms, socket); > > - create_fdt_socket_cpus(fdt, (&s->soc[socket])->harts, socket, > - s->soc[socket].num_harts, > - s->soc[socket].hartid_base, > - &phandle, intc_phandles, numa_enabled, > - is_32_bit); > + riscv_create_fdt_socket_cpus(fdt, (&s->soc[socket])->harts, socket, > + s->soc[socket].num_harts, > + s->soc[socket].hartid_base, > + &phandle, intc_phandles, numa_enabled, > + is_32_bit); > > - create_fdt_socket_memory(fdt, memaddr, memsize, socket, > - riscv_numa_enabled(ms)); > + riscv_create_fdt_socket_memory(fdt, memaddr, memsize, socket, > + riscv_numa_enabled(ms)); > > clint_addr = memmap[SPIKE_CLINT].base + > (memmap[SPIKE_CLINT].size * socket); > - create_fdt_socket_clint(fdt, clint_addr, memmap[SPIKE_CLINT].size, > - socket, intc_phandles, > - s->soc[socket].num_harts, numa_enabled); > + riscv_create_fdt_socket_clint(fdt, clint_addr, > + memmap[SPIKE_CLINT].size, socket, > + intc_phandles, s->soc[socket].num_harts, > + numa_enabled); > } > > riscv_socket_fdt_write_distance_matrix(ms); > diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c > index babce2b680..812051a11f 100644 > --- a/hw/riscv/tt_atlantis.c > +++ b/hw/riscv/tt_atlantis.c > @@ -91,16 +91,17 @@ static void create_fdt_memory(TTAtlantisState *s) > size_hi = MACHINE(s)->ram_size - size_lo; > } > > - create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_LO].base, size_lo, > - 0, false); > + riscv_create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_LO].base, > + size_lo, 0, false); > if (size_hi) { > /* > * The first part of the HI address is aliased at the LO address > * so do not include that as usable memory. Is there any way > * (or good reason) to describe that aliasing 2GB with DT? > */ > - create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_HI].base + size_lo, > - size_hi, 0, false); > + riscv_create_fdt_socket_memory(fdt, > + s->memmap[TT_ATL_DDR_HI].base + size_lo, > + size_hi, 0, false); > } > } > > @@ -225,11 +226,11 @@ static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap, > void *fdt = MACHINE(s)->fdt; > g_autofree uint32_t *intc_phandles = g_new0(uint32_t, ms->smp.cpus); > > - fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); > + riscv_fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); > > - create_fdt_socket_cpus(fdt, s->soc.harts, 0, s->soc.num_harts, > - s->soc.hartid_base, &fdt_phandle, intc_phandles, > - false, false); > + riscv_create_fdt_socket_cpus(fdt, s->soc.harts, 0, s->soc.num_harts, > + s->soc.hartid_base, &fdt_phandle, > + intc_phandles, false, false); > > create_fdt_memory(s); > > @@ -367,8 +368,9 @@ static void create_fdt(TTAtlantisState *s) > { > MachineState *ms = MACHINE(s); > > - ms->fdt = create_board_device_tree("Tenstorrent Atlantis RISC-V Machine", > - "tenstorrent,atlantis", &s->fdt_size); > + ms->fdt = riscv_create_board_device_tree( > + "Tenstorrent Atlantis RISC-V Machine", > + "tenstorrent,atlantis", &s->fdt_size); > > qemu_fdt_add_subnode(ms->fdt, "/chosen"); > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 329ccdb5a7..b796220fc2 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -360,12 +360,12 @@ static void create_fdt_socket_plic(RISCVVirtState *s, > > plic_phandles[socket] = (*phandle)++; > > - create_fdt_plic(ms->fdt, plic_addr, s->memmap[VIRT_PLIC].size, > - plic_phandles[socket], FDT_PLIC_INT_CELLS, > - FDT_PLIC_ADDR_CELLS, plic_cells, > - cells_length * sizeof(uint32_t), > - VIRT_IRQCHIP_NUM_SOURCES - 1, > - numa_enabled, socket); > + riscv_create_fdt_plic(ms->fdt, plic_addr, s->memmap[VIRT_PLIC].size, > + plic_phandles[socket], FDT_PLIC_INT_CELLS, > + FDT_PLIC_ADDR_CELLS, plic_cells, > + cells_length * sizeof(uint32_t), > + VIRT_IRQCHIP_NUM_SOURCES - 1, > + numa_enabled, socket); > > if (!socket) { > platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, > @@ -601,7 +601,7 @@ static void create_fdt_sockets(RISCVVirtState *s, > bool numa_enabled = riscv_numa_enabled(ms); > bool is_32_bit = riscv_is_32bit(&s->soc[0]); > > - fdt_create_cpu_socket_subnode(ms->fdt, > + riscv_fdt_create_cpu_socket_subnode(ms->fdt, > kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) : > RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); > > @@ -615,14 +615,14 @@ static void create_fdt_sockets(RISCVVirtState *s, > > phandle_pos -= s->soc[socket].num_harts; > > - create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, socket, > - s->soc[socket].num_harts, > - s->soc[socket].hartid_base, > - phandle, &intc_phandles[phandle_pos], > - numa_enabled, is_32_bit); > + riscv_create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, socket, > + s->soc[socket].num_harts, > + s->soc[socket].hartid_base, > + phandle, &intc_phandles[phandle_pos], > + numa_enabled, is_32_bit); > > - create_fdt_socket_memory(ms->fdt, memaddr, memsize, > - socket, riscv_numa_enabled(ms)); > + riscv_create_fdt_socket_memory(ms->fdt, memaddr, memsize, > + socket, riscv_numa_enabled(ms)); > > if (virt_aclint_allowed() && s->have_aclint) { > create_fdt_socket_aclint(s, socket, > @@ -631,10 +631,11 @@ static void create_fdt_sockets(RISCVVirtState *s, > hwaddr clintaddr = s->memmap[VIRT_CLINT].base + > s->memmap[VIRT_CLINT].size * socket; > > - create_fdt_socket_clint(ms->fdt, clintaddr, > - s->memmap[VIRT_CLINT].size, > - socket, &intc_phandles[phandle_pos], > - s->soc[socket].num_harts, numa_enabled); > + riscv_create_fdt_socket_clint(ms->fdt, clintaddr, > + s->memmap[VIRT_CLINT].size, > + socket, &intc_phandles[phandle_pos], > + s->soc[socket].num_harts, > + numa_enabled); > } > } > > @@ -1021,8 +1022,9 @@ static void create_fdt(RISCVVirtState *s) > uint8_t rng_seed[32]; > g_autofree char *name = NULL; > > - ms->fdt = create_board_device_tree("riscv-virtio,qemu", "riscv-virtio", > - &s->fdt_size); > + ms->fdt = riscv_create_board_device_tree("riscv-virtio,qemu", > + "riscv-virtio", > + &s->fdt_size); > > /* > * The "/soc/pci@..." node is needed for PCIE hotplugs > diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h > index 1729a6abc6..371971d79d 100644 > --- a/include/hw/riscv/fdt-common.h > +++ b/include/hw/riscv/fdt-common.h > @@ -11,29 +11,31 @@ > > #include "target/riscv/cpu.h" > > -void *create_board_device_tree(const char *model, const char *compatible, > - int *fdt_size); > -void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, > - int socket_id, bool numa_enabled); > -void create_fdt_clint(void *fdt, hwaddr addr, uint64_t size, > - uint32_t *intc_phandles, int num_harts); > -void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, > - int socket_id, uint32_t *intc_phandles, > - int num_harts, bool numa_enabled); > -void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency); > -void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, > - int socket_id, int num_harts_socket, > - int socket_hartid_base, uint32_t *phandle, > - uint32_t *intc_phandles, bool numa_enabled, > - bool is_32_bit); > -void create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, > - int cpu_id, int socket_id, > +void *riscv_create_board_device_tree(const char *model, const char *compatible, > + int *fdt_size); > +void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, > + int socket_id, bool numa_enabled); > +void riscv_create_fdt_clint(void *fdt, hwaddr addr, uint64_t size, > + uint32_t *intc_phandles, int num_harts); > +void riscv_create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, > + int socket_id, uint32_t *intc_phandles, > + int num_harts, bool numa_enabled); > +void riscv_fdt_create_cpu_socket_subnode(void *fdt, > + uint64_t timebase_frequency); > +void riscv_create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, > + int socket_id, int num_harts_socket, > int socket_hartid_base, uint32_t *phandle, > - uint32_t *intc_phandles); > -void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, > - uint32_t plic_phandle, uint32_t int_cells, > - uint32_t addr_cells, uint32_t *plic_cells, > - uint32_t cells_size, uint32_t ndev_sources, > - bool numa_enabled, int socket); > + uint32_t *intc_phandles, bool numa_enabled, > + bool is_32_bit); > +void riscv_create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, > + int cpu_id, int socket_id, > + int socket_hartid_base, > + uint32_t *phandle, > + uint32_t *intc_phandles); > +void riscv_create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, > + uint32_t plic_phandle, uint32_t int_cells, > + uint32_t addr_cells, uint32_t *plic_cells, > + uint32_t cells_size, uint32_t ndev_sources, > + bool numa_enabled, int socket); > void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name); > #endif > -- > 2.43.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3C50C61DB9 for ; Fri, 28 Aug 2026 02:55:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzmjw-0001ji-AJ; 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envelope-from=chao.liu@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Chao Liu From: Chao Liu via qemu development Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Aug 27, 2026 at 07:25:54PM +0800, Daniel Henrique Barboza wrote: > Given that the helpers are public API we should prefix them with > "riscv_" to avoid conflicts when linking with different targets in the > future, i.e. we should not use generic names like > "create_fdt_socket_memory". > > Despite the amount of lines this is a mechanical change and no real > FDT changes are intended. > > Suggested-by: Philippe Mathieu-Daudé > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Thanks, Chao > --- > hw/riscv/fdt-common.c | 45 ++++++++++++++++---------------- > hw/riscv/sifive_u.c | 34 +++++++++++++------------ > hw/riscv/spike.c | 30 ++++++++++++---------- > hw/riscv/tt_atlantis.c | 22 ++++++++-------- > hw/riscv/virt.c | 42 +++++++++++++++--------------- > include/hw/riscv/fdt-common.h | 48 ++++++++++++++++++----------------- > 6 files changed, 117 insertions(+), 104 deletions(-) > > diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c > index aa143a618b..3a8da03cfb 100644 > --- a/hw/riscv/fdt-common.c > +++ b/hw/riscv/fdt-common.c > @@ -14,8 +14,8 @@ > #include "hw/riscv/fdt-common.h" > #include "target/riscv/cpu_bits.h" > > -void *create_board_device_tree(const char *model, const char *compatible, > - int *fdt_size) > +void *riscv_create_board_device_tree(const char *model, const char *compatible, > + int *fdt_size) > { > void *fdt = create_device_tree(fdt_size); > > @@ -38,8 +38,8 @@ void *create_board_device_tree(const char *model, const char *compatible, > return fdt; > } > > -void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, > - int socket_id, bool numa_enabled) > +void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, > + int socket_id, bool numa_enabled) > { > g_autofree char *mem_name = g_strdup_printf("/memory@%"HWADDR_PRIx, addr); > > @@ -52,9 +52,9 @@ void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, > } > } > > -void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, > - int socket_id, uint32_t *intc_phandles, > - int num_harts, bool numa_enabled) > +void riscv_create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, > + int socket_id, uint32_t *intc_phandles, > + int num_harts, bool numa_enabled) > { > g_autofree uint32_t *clint_cells = g_new0(uint32_t, num_harts * 4); > g_autofree char *clint_name = NULL; > @@ -84,7 +84,8 @@ void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, > } > } > > -void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency) > +void riscv_fdt_create_cpu_socket_subnode(void *fdt, > + uint64_t timebase_frequency) > { > qemu_fdt_add_subnode(fdt, "/cpus"); > qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", > @@ -169,11 +170,11 @@ create_fdt_socket_cpu_internal(void *fdt, char *clust_name, RISCVCPU *cpu_ptr, > qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); > } > > -void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, > - int socket_id, int num_harts_socket, > - int socket_hartid_base, uint32_t *phandle, > - uint32_t *intc_phandles, bool numa_enabled, > - bool is_32_bit) > +void riscv_create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, > + int socket_id, int num_harts_socket, > + int socket_hartid_base, uint32_t *phandle, > + uint32_t *intc_phandles, bool numa_enabled, > + bool is_32_bit) > { > g_autofree char *clust_name = NULL; > > @@ -191,21 +192,21 @@ void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, > } > > void > -create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, > - int cpu_id, int socket_id, > - int socket_hartid_base, uint32_t *phandle, > - uint32_t *intc_phandles) > +riscv_create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, > + int cpu_id, int socket_id, > + int socket_hartid_base, uint32_t *phandle, > + uint32_t *intc_phandles) > { > create_fdt_socket_cpu_internal(fdt, clust_name, NULL, cpu_id, > socket_id, socket_hartid_base, > phandle, intc_phandles, false, false); > } > > -void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, > - uint32_t plic_phandle, uint32_t int_cells, > - uint32_t addr_cells, uint32_t *plic_cells, > - uint32_t cells_size, uint32_t ndev_sources, > - bool numa_enabled, int socket_id) > +void riscv_create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, > + uint32_t plic_phandle, uint32_t int_cells, > + uint32_t addr_cells, uint32_t *plic_cells, > + uint32_t cells_size, uint32_t ndev_sources, > + bool numa_enabled, int socket_id) > { > g_autofree char *nodename = NULL; > static const char * const plic_compat[2] = { > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 57a57c96e1..852c48c056 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -108,8 +108,10 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > g_autofree uint32_t *intc_phandles = g_new0(uint32_t, ms->smp.cpus); > g_autofree char *clust_name = NULL; > > - fdt = ms->fdt = create_board_device_tree("SiFive HiFive Unleashed A00", > - "sifive,hifive-unleashed-a00", &s->fdt_size); > + fdt = ms->fdt = riscv_create_board_device_tree( > + "SiFive HiFive Unleashed A00", > + "sifive,hifive-unleashed-a00", > + &s->fdt_size); > > hfclk_phandle = phandle++; > nodename = g_strdup_printf("/hfclk"); > @@ -133,10 +135,10 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); > g_free(nodename); > > - create_fdt_socket_memory(fdt, memmap[SIFIVE_U_DEV_DRAM].base, > - ms->ram_size, 0, false); > + riscv_create_fdt_socket_memory(fdt, memmap[SIFIVE_U_DEV_DRAM].base, > + ms->ram_size, 0, false); > > - fdt_create_cpu_socket_subnode(fdt, CLINT_TIMEBASE_FREQ); > + riscv_fdt_create_cpu_socket_subnode(fdt, CLINT_TIMEBASE_FREQ); > > clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", 0); > qemu_fdt_add_subnode(fdt, clust_name); > @@ -157,15 +159,15 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename); > } > > - create_fdt_socket_cpu_sifive(fdt, clust_name, cpu, 0, 0, > - &phandle, intc_phandles); > + riscv_create_fdt_socket_cpu_sifive(fdt, clust_name, cpu, 0, 0, > + &phandle, intc_phandles); > > g_free(nodename); > } > > - create_fdt_socket_clint(fdt, memmap[SIFIVE_U_DEV_CLINT].base, > - memmap[SIFIVE_U_DEV_CLINT].size, 0, > - intc_phandles, ms->smp.cpus, false); > + riscv_create_fdt_socket_clint(fdt, memmap[SIFIVE_U_DEV_CLINT].base, > + memmap[SIFIVE_U_DEV_CLINT].size, 0, > + intc_phandles, ms->smp.cpus, false); > > nodename = g_strdup_printf("/soc/otp@%lx", > (long)memmap[SIFIVE_U_DEV_OTP].base); > @@ -209,12 +211,12 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > } > } > > - create_fdt_plic(fdt, memmap[SIFIVE_U_DEV_PLIC].base, > - memmap[SIFIVE_U_DEV_PLIC].size, > - plic_phandle, SIFIVE_U_PLIC_INT_CELLS, > - SIFIVE_U_PLIC_ADDR_CELLS, cells, > - cells_length * sizeof(uint32_t), > - SIFIVE_U_PLIC_NUM_SOURCES - 1, false, 0); > + riscv_create_fdt_plic(fdt, memmap[SIFIVE_U_DEV_PLIC].base, > + memmap[SIFIVE_U_DEV_PLIC].size, > + plic_phandle, SIFIVE_U_PLIC_INT_CELLS, > + SIFIVE_U_PLIC_ADDR_CELLS, cells, > + cells_length * sizeof(uint32_t), > + SIFIVE_U_PLIC_NUM_SOURCES - 1, false, 0); > g_free(cells); > > gpio_phandle = phandle++; > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 630b65f569..8d7e93807c 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -61,8 +61,10 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > uint32_t phandle = 1; > bool numa_enabled = riscv_numa_enabled(ms); > > - fdt = ms->fdt = create_board_device_tree("ucbbar,spike-bare,qemu", > - "ucbbar,spike-bare-dev", &fdt_size); > + fdt = ms->fdt = riscv_create_board_device_tree( > + "ucbbar,spike-bare,qemu", > + "ucbbar,spike-bare-dev", > + &fdt_size); > > qemu_fdt_add_subnode(fdt, "/htif"); > qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); > @@ -71,7 +73,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); > } > > - fdt_create_cpu_socket_subnode(fdt, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); > + riscv_fdt_create_cpu_socket_subnode(fdt, > + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); > > for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) { > g_autofree uint32_t *intc_phandles = g_new0(uint32_t, > @@ -80,20 +83,21 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > riscv_socket_mem_offset(ms, socket); > uint64_t memsize = riscv_socket_mem_size(ms, socket); > > - create_fdt_socket_cpus(fdt, (&s->soc[socket])->harts, socket, > - s->soc[socket].num_harts, > - s->soc[socket].hartid_base, > - &phandle, intc_phandles, numa_enabled, > - is_32_bit); > + riscv_create_fdt_socket_cpus(fdt, (&s->soc[socket])->harts, socket, > + s->soc[socket].num_harts, > + s->soc[socket].hartid_base, > + &phandle, intc_phandles, numa_enabled, > + is_32_bit); > > - create_fdt_socket_memory(fdt, memaddr, memsize, socket, > - riscv_numa_enabled(ms)); > + riscv_create_fdt_socket_memory(fdt, memaddr, memsize, socket, > + riscv_numa_enabled(ms)); > > clint_addr = memmap[SPIKE_CLINT].base + > (memmap[SPIKE_CLINT].size * socket); > - create_fdt_socket_clint(fdt, clint_addr, memmap[SPIKE_CLINT].size, > - socket, intc_phandles, > - s->soc[socket].num_harts, numa_enabled); > + riscv_create_fdt_socket_clint(fdt, clint_addr, > + memmap[SPIKE_CLINT].size, socket, > + intc_phandles, s->soc[socket].num_harts, > + numa_enabled); > } > > riscv_socket_fdt_write_distance_matrix(ms); > diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c > index babce2b680..812051a11f 100644 > --- a/hw/riscv/tt_atlantis.c > +++ b/hw/riscv/tt_atlantis.c > @@ -91,16 +91,17 @@ static void create_fdt_memory(TTAtlantisState *s) > size_hi = MACHINE(s)->ram_size - size_lo; > } > > - create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_LO].base, size_lo, > - 0, false); > + riscv_create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_LO].base, > + size_lo, 0, false); > if (size_hi) { > /* > * The first part of the HI address is aliased at the LO address > * so do not include that as usable memory. Is there any way > * (or good reason) to describe that aliasing 2GB with DT? > */ > - create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_HI].base + size_lo, > - size_hi, 0, false); > + riscv_create_fdt_socket_memory(fdt, > + s->memmap[TT_ATL_DDR_HI].base + size_lo, > + size_hi, 0, false); > } > } > > @@ -225,11 +226,11 @@ static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap, > void *fdt = MACHINE(s)->fdt; > g_autofree uint32_t *intc_phandles = g_new0(uint32_t, ms->smp.cpus); > > - fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); > + riscv_fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); > > - create_fdt_socket_cpus(fdt, s->soc.harts, 0, s->soc.num_harts, > - s->soc.hartid_base, &fdt_phandle, intc_phandles, > - false, false); > + riscv_create_fdt_socket_cpus(fdt, s->soc.harts, 0, s->soc.num_harts, > + s->soc.hartid_base, &fdt_phandle, > + intc_phandles, false, false); > > create_fdt_memory(s); > > @@ -367,8 +368,9 @@ static void create_fdt(TTAtlantisState *s) > { > MachineState *ms = MACHINE(s); > > - ms->fdt = create_board_device_tree("Tenstorrent Atlantis RISC-V Machine", > - "tenstorrent,atlantis", &s->fdt_size); > + ms->fdt = riscv_create_board_device_tree( > + "Tenstorrent Atlantis RISC-V Machine", > + "tenstorrent,atlantis", &s->fdt_size); > > qemu_fdt_add_subnode(ms->fdt, "/chosen"); > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 329ccdb5a7..b796220fc2 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -360,12 +360,12 @@ static void create_fdt_socket_plic(RISCVVirtState *s, > > plic_phandles[socket] = (*phandle)++; > > - create_fdt_plic(ms->fdt, plic_addr, s->memmap[VIRT_PLIC].size, > - plic_phandles[socket], FDT_PLIC_INT_CELLS, > - FDT_PLIC_ADDR_CELLS, plic_cells, > - cells_length * sizeof(uint32_t), > - VIRT_IRQCHIP_NUM_SOURCES - 1, > - numa_enabled, socket); > + riscv_create_fdt_plic(ms->fdt, plic_addr, s->memmap[VIRT_PLIC].size, > + plic_phandles[socket], FDT_PLIC_INT_CELLS, > + FDT_PLIC_ADDR_CELLS, plic_cells, > + cells_length * sizeof(uint32_t), > + VIRT_IRQCHIP_NUM_SOURCES - 1, > + numa_enabled, socket); > > if (!socket) { > platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, > @@ -601,7 +601,7 @@ static void create_fdt_sockets(RISCVVirtState *s, > bool numa_enabled = riscv_numa_enabled(ms); > bool is_32_bit = riscv_is_32bit(&s->soc[0]); > > - fdt_create_cpu_socket_subnode(ms->fdt, > + riscv_fdt_create_cpu_socket_subnode(ms->fdt, > kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) : > RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); > > @@ -615,14 +615,14 @@ static void create_fdt_sockets(RISCVVirtState *s, > > phandle_pos -= s->soc[socket].num_harts; > > - create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, socket, > - s->soc[socket].num_harts, > - s->soc[socket].hartid_base, > - phandle, &intc_phandles[phandle_pos], > - numa_enabled, is_32_bit); > + riscv_create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, socket, > + s->soc[socket].num_harts, > + s->soc[socket].hartid_base, > + phandle, &intc_phandles[phandle_pos], > + numa_enabled, is_32_bit); > > - create_fdt_socket_memory(ms->fdt, memaddr, memsize, > - socket, riscv_numa_enabled(ms)); > + riscv_create_fdt_socket_memory(ms->fdt, memaddr, memsize, > + socket, riscv_numa_enabled(ms)); > > if (virt_aclint_allowed() && s->have_aclint) { > create_fdt_socket_aclint(s, socket, > @@ -631,10 +631,11 @@ static void create_fdt_sockets(RISCVVirtState *s, > hwaddr clintaddr = s->memmap[VIRT_CLINT].base + > s->memmap[VIRT_CLINT].size * socket; > > - create_fdt_socket_clint(ms->fdt, clintaddr, > - s->memmap[VIRT_CLINT].size, > - socket, &intc_phandles[phandle_pos], > - s->soc[socket].num_harts, numa_enabled); > + riscv_create_fdt_socket_clint(ms->fdt, clintaddr, > + s->memmap[VIRT_CLINT].size, > + socket, &intc_phandles[phandle_pos], > + s->soc[socket].num_harts, > + numa_enabled); > } > } > > @@ -1021,8 +1022,9 @@ static void create_fdt(RISCVVirtState *s) > uint8_t rng_seed[32]; > g_autofree char *name = NULL; > > - ms->fdt = create_board_device_tree("riscv-virtio,qemu", "riscv-virtio", > - &s->fdt_size); > + ms->fdt = riscv_create_board_device_tree("riscv-virtio,qemu", > + "riscv-virtio", > + &s->fdt_size); > > /* > * The "/soc/pci@..." node is needed for PCIE hotplugs > diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h > index 1729a6abc6..371971d79d 100644 > --- a/include/hw/riscv/fdt-common.h > +++ b/include/hw/riscv/fdt-common.h > @@ -11,29 +11,31 @@ > > #include "target/riscv/cpu.h" > > -void *create_board_device_tree(const char *model, const char *compatible, > - int *fdt_size); > -void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, > - int socket_id, bool numa_enabled); > -void create_fdt_clint(void *fdt, hwaddr addr, uint64_t size, > - uint32_t *intc_phandles, int num_harts); > -void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, > - int socket_id, uint32_t *intc_phandles, > - int num_harts, bool numa_enabled); > -void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency); > -void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, > - int socket_id, int num_harts_socket, > - int socket_hartid_base, uint32_t *phandle, > - uint32_t *intc_phandles, bool numa_enabled, > - bool is_32_bit); > -void create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, > - int cpu_id, int socket_id, > +void *riscv_create_board_device_tree(const char *model, const char *compatible, > + int *fdt_size); > +void riscv_create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, > + int socket_id, bool numa_enabled); > +void riscv_create_fdt_clint(void *fdt, hwaddr addr, uint64_t size, > + uint32_t *intc_phandles, int num_harts); > +void riscv_create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, > + int socket_id, uint32_t *intc_phandles, > + int num_harts, bool numa_enabled); > +void riscv_fdt_create_cpu_socket_subnode(void *fdt, > + uint64_t timebase_frequency); > +void riscv_create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, > + int socket_id, int num_harts_socket, > int socket_hartid_base, uint32_t *phandle, > - uint32_t *intc_phandles); > -void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, > - uint32_t plic_phandle, uint32_t int_cells, > - uint32_t addr_cells, uint32_t *plic_cells, > - uint32_t cells_size, uint32_t ndev_sources, > - bool numa_enabled, int socket); > + uint32_t *intc_phandles, bool numa_enabled, > + bool is_32_bit); > +void riscv_create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, > + int cpu_id, int socket_id, > + int socket_hartid_base, > + uint32_t *phandle, > + uint32_t *intc_phandles); > +void riscv_create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, > + uint32_t plic_phandle, uint32_t int_cells, > + uint32_t addr_cells, uint32_t *plic_cells, > + uint32_t cells_size, uint32_t ndev_sources, > + bool numa_enabled, int socket); > void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name); > #endif > -- > 2.43.0 >