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envelope-from=chao.liu@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Chao Liu From: Chao Liu via qemu development Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Aug 27, 2026 at 07:25:57PM +0800, Daniel Henrique Barboza wrote: > Both the 'virt' board and the future 'riscv-server-ref' boards uses an > iommu-sys device that is declared in the DT. Create a helper to > encapsulate the logic and avoid copy/pasting stuff between boards. > > The helper will return the iommu phandle value instead of returning void > and writing the used phandle in an extra argument. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Chao Liu Thanks, Chao > --- > hw/riscv/fdt-common.c | 35 ++++++++++++++++++++++++ > hw/riscv/virt.c | 50 ++++++----------------------------- > include/hw/riscv/fdt-common.h | 5 ++++ > 3 files changed, 48 insertions(+), 42 deletions(-) > > diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c > index eac5ca9322..88589330fb 100644 > --- a/hw/riscv/fdt-common.c > +++ b/hw/riscv/fdt-common.c > @@ -13,6 +13,8 @@ > #include "hw/core/boards.h" > #include "hw/riscv/fdt-common.h" > #include "target/riscv/cpu_bits.h" > +#include "hw/riscv/riscv-iommu-bits.h" > +#include "hw/riscv/iommu.h" > > void *riscv_create_board_device_tree(const char *model, const char *compatible, > int *fdt_size) > @@ -349,3 +351,36 @@ void riscv_create_fdt_syscon(void *fdt, uint32_t *next_phandle, > qemu_fdt_setprop_cell(fdt, name, "value", poweroff); > g_free(name); > } > + > +uint32_t riscv_create_fdt_riscv_iommu_sys(void *fdt, hwaddr addr, hwaddr size, > + uint32_t *next_phandle, > + uint32_t irq_chip, > + uint32_t msi_phandle, > + uint32_t iommu_sys_irq) > +{ > + const char comp[] = "riscv,iommu"; > + g_autofree char *iommu_node = NULL; > + uint32_t iommu_phandle; > + > + iommu_node = g_strdup_printf("/soc/iommu@%"HWADDR_PRIx, addr); > + qemu_fdt_add_subnode(fdt, iommu_node); > + > + qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); > + qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); > + > + iommu_phandle = next_phandle ? (*next_phandle)++ : qemu_fdt_alloc_phandle(fdt); > + qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); > + > + qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size); > + qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); > + > + qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", > + iommu_sys_irq + RISCV_IOMMU_INTR_CQ, FDT_IRQ_TYPE_EDGE_LOW, > + iommu_sys_irq + RISCV_IOMMU_INTR_FQ, FDT_IRQ_TYPE_EDGE_LOW, > + iommu_sys_irq + RISCV_IOMMU_INTR_PM, FDT_IRQ_TYPE_EDGE_LOW, > + iommu_sys_irq + RISCV_IOMMU_INTR_PQ, FDT_IRQ_TYPE_EDGE_LOW); > + > + qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); > + > + return iommu_phandle; > +} > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index ab6c53c78a..8a165f4d9e 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -869,46 +869,6 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) > bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); > } > > -static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, > - uint32_t msi_phandle, > - uint32_t *iommu_sys_phandle) > -{ > - const char comp[] = "riscv,iommu"; > - void *fdt = MACHINE(s)->fdt; > - uint32_t iommu_phandle; > - g_autofree char *iommu_node = NULL; > - hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base; > - hwaddr size = s->memmap[VIRT_IOMMU_SYS].size; > - uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = { > - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, > - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, > - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, > - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, > - }; > - > - iommu_node = g_strdup_printf("/soc/iommu@%x", > - (unsigned int) s->memmap[VIRT_IOMMU_SYS].base); > - iommu_phandle = qemu_fdt_alloc_phandle(fdt); > - qemu_fdt_add_subnode(fdt, iommu_node); > - > - qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); > - qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); > - qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); > - > - qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size); > - qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); > - > - qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", > - iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, > - iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, > - iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, > - iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); > - > - qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); > - > - *iommu_sys_phandle = iommu_phandle; > -} > - > static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) > { > const char comp[] = "riscv,pci-iommu"; > @@ -947,8 +907,14 @@ static void finalize_fdt(RISCVVirtState *s) > create_fdt_virtio(s, irq_virtio_phandle); > > if (virt_is_iommu_sys_enabled(s)) { > - create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, > - &iommu_sys_phandle); > + iommu_sys_phandle = > + riscv_create_fdt_riscv_iommu_sys(MACHINE(s)->fdt, > + s->memmap[VIRT_IOMMU_SYS].base, > + s->memmap[VIRT_IOMMU_SYS].size, > + &phandle, > + irq_mmio_phandle, > + msi_pcie_phandle, > + IOMMU_SYS_IRQ); > } > create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, > iommu_sys_phandle); > diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h > index e377682b32..65711468b8 100644 > --- a/include/hw/riscv/fdt-common.h > +++ b/include/hw/riscv/fdt-common.h > @@ -43,4 +43,9 @@ void riscv_create_fdt_syscon(void *fdt, uint32_t *next_phandle, > hwaddr addr, hwaddr size, > uint32_t reboot, uint32_t poweroff, > bool sifive_test_compat); > +uint32_t riscv_create_fdt_riscv_iommu_sys(void *fdt, hwaddr addr, hwaddr size, > + uint32_t *next_phandle, > + uint32_t irq_chip, > + uint32_t msi_phandle, > + uint32_t iommu_sys_irq); > #endif > -- > 2.43.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72CE1C61DC4 for ; Fri, 28 Aug 2026 02:58:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wzmn7-0004Ha-GT; Thu, 27 Aug 2026 22:58:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzmn5-0004Ga-0u; Thu, 27 Aug 2026 22:58:03 -0400 Received: from mail-japanwestazlp170120003.outbound.protection.outlook.com ([2a01:111:f403:c406::3] helo=OS8PR02CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wzmn3-00087b-5j; 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envelope-from=chao.liu@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Chao Liu From: Chao Liu via Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Thu, Aug 27, 2026 at 07:25:57PM +0800, Daniel Henrique Barboza wrote: > Both the 'virt' board and the future 'riscv-server-ref' boards uses an > iommu-sys device that is declared in the DT. Create a helper to > encapsulate the logic and avoid copy/pasting stuff between boards. > > The helper will return the iommu phandle value instead of returning void > and writing the used phandle in an extra argument. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Chao Liu Thanks, Chao > --- > hw/riscv/fdt-common.c | 35 ++++++++++++++++++++++++ > hw/riscv/virt.c | 50 ++++++----------------------------- > include/hw/riscv/fdt-common.h | 5 ++++ > 3 files changed, 48 insertions(+), 42 deletions(-) > > diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c > index eac5ca9322..88589330fb 100644 > --- a/hw/riscv/fdt-common.c > +++ b/hw/riscv/fdt-common.c > @@ -13,6 +13,8 @@ > #include "hw/core/boards.h" > #include "hw/riscv/fdt-common.h" > #include "target/riscv/cpu_bits.h" > +#include "hw/riscv/riscv-iommu-bits.h" > +#include "hw/riscv/iommu.h" > > void *riscv_create_board_device_tree(const char *model, const char *compatible, > int *fdt_size) > @@ -349,3 +351,36 @@ void riscv_create_fdt_syscon(void *fdt, uint32_t *next_phandle, > qemu_fdt_setprop_cell(fdt, name, "value", poweroff); > g_free(name); > } > + > +uint32_t riscv_create_fdt_riscv_iommu_sys(void *fdt, hwaddr addr, hwaddr size, > + uint32_t *next_phandle, > + uint32_t irq_chip, > + uint32_t msi_phandle, > + uint32_t iommu_sys_irq) > +{ > + const char comp[] = "riscv,iommu"; > + g_autofree char *iommu_node = NULL; > + uint32_t iommu_phandle; > + > + iommu_node = g_strdup_printf("/soc/iommu@%"HWADDR_PRIx, addr); > + qemu_fdt_add_subnode(fdt, iommu_node); > + > + qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); > + qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); > + > + iommu_phandle = next_phandle ? (*next_phandle)++ : qemu_fdt_alloc_phandle(fdt); > + qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); > + > + qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size); > + qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); > + > + qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", > + iommu_sys_irq + RISCV_IOMMU_INTR_CQ, FDT_IRQ_TYPE_EDGE_LOW, > + iommu_sys_irq + RISCV_IOMMU_INTR_FQ, FDT_IRQ_TYPE_EDGE_LOW, > + iommu_sys_irq + RISCV_IOMMU_INTR_PM, FDT_IRQ_TYPE_EDGE_LOW, > + iommu_sys_irq + RISCV_IOMMU_INTR_PQ, FDT_IRQ_TYPE_EDGE_LOW); > + > + qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); > + > + return iommu_phandle; > +} > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index ab6c53c78a..8a165f4d9e 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -869,46 +869,6 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) > bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); > } > > -static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, > - uint32_t msi_phandle, > - uint32_t *iommu_sys_phandle) > -{ > - const char comp[] = "riscv,iommu"; > - void *fdt = MACHINE(s)->fdt; > - uint32_t iommu_phandle; > - g_autofree char *iommu_node = NULL; > - hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base; > - hwaddr size = s->memmap[VIRT_IOMMU_SYS].size; > - uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = { > - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, > - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, > - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, > - IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, > - }; > - > - iommu_node = g_strdup_printf("/soc/iommu@%x", > - (unsigned int) s->memmap[VIRT_IOMMU_SYS].base); > - iommu_phandle = qemu_fdt_alloc_phandle(fdt); > - qemu_fdt_add_subnode(fdt, iommu_node); > - > - qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); > - qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); > - qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); > - > - qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size); > - qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); > - > - qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", > - iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, > - iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, > - iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, > - iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); > - > - qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); > - > - *iommu_sys_phandle = iommu_phandle; > -} > - > static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) > { > const char comp[] = "riscv,pci-iommu"; > @@ -947,8 +907,14 @@ static void finalize_fdt(RISCVVirtState *s) > create_fdt_virtio(s, irq_virtio_phandle); > > if (virt_is_iommu_sys_enabled(s)) { > - create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, > - &iommu_sys_phandle); > + iommu_sys_phandle = > + riscv_create_fdt_riscv_iommu_sys(MACHINE(s)->fdt, > + s->memmap[VIRT_IOMMU_SYS].base, > + s->memmap[VIRT_IOMMU_SYS].size, > + &phandle, > + irq_mmio_phandle, > + msi_pcie_phandle, > + IOMMU_SYS_IRQ); > } > create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, > iommu_sys_phandle); > diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h > index e377682b32..65711468b8 100644 > --- a/include/hw/riscv/fdt-common.h > +++ b/include/hw/riscv/fdt-common.h > @@ -43,4 +43,9 @@ void riscv_create_fdt_syscon(void *fdt, uint32_t *next_phandle, > hwaddr addr, hwaddr size, > uint32_t reboot, uint32_t poweroff, > bool sifive_test_compat); > +uint32_t riscv_create_fdt_riscv_iommu_sys(void *fdt, hwaddr addr, hwaddr size, > + uint32_t *next_phandle, > + uint32_t irq_chip, > + uint32_t msi_phandle, > + uint32_t iommu_sys_irq); > #endif > -- > 2.43.0 >