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envelope-from=chao.liu@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Chao Liu From: Chao Liu via Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Fri, Aug 28, 2026 at 05:39:14PM +0800, Daniel Henrique Barboza wrote: > There will be code repetition instances added by the 'riscv-server-ref' > board w.r.t device creation and initialization. Instead of waiting for > that code to land we're adding helpers beforehand. The idea is to make > the new board code shorter and more palatable for reviewers. > > A new 'device-common' file is created for such helpers. We'll start > with the platform bus, a nice piece of software that only the 'virt' > board uses so far, and the 'riscv-server-ref' will use to support TPM > devices. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Chao Liu Thanks, Chao > --- > hw/riscv/device-common.c | 48 ++++++++++++++++++++++++++++++++ > hw/riscv/meson.build | 1 + > hw/riscv/virt.c | 30 +++----------------- > include/hw/riscv/device-common.h | 19 +++++++++++++ > 4 files changed, 72 insertions(+), 26 deletions(-) > create mode 100644 hw/riscv/device-common.c > create mode 100644 include/hw/riscv/device-common.h > > diff --git a/hw/riscv/device-common.c b/hw/riscv/device-common.c > new file mode 100644 > index 0000000000..d3c68a9e71 > --- /dev/null > +++ b/hw/riscv/device-common.c > @@ -0,0 +1,48 @@ > +/* > + * RISC-V board helpers for FDT generation. > + * > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > + > +#include "hw/riscv/device-common.h" > + > +#include "hw/core/platform-bus.h" > +#include "hw/core/qdev.h" > +#include "hw/core/qdev-properties.h" > +#include "hw/core/sysbus.h" > +#include "qapi/error.h" > +#include "system/address-spaces.h" > +#include "system/memory.h" > + > + > +DeviceState *riscv_create_platform_bus(DeviceState *irqchip, > + const MemMapEntry *platform_bus_mem, > + int platform_bus_base_irq, > + int platform_bus_num_irqs) > +{ > + MemoryRegion *sysmem = get_system_memory(); > + DeviceState *dev; > + SysBusDevice *sysbus; > + > + dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); > + dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); > + qdev_prop_set_uint32(dev, "num_irqs", platform_bus_num_irqs); > + qdev_prop_set_uint32(dev, "mmio_size", platform_bus_mem->size); > + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > + > + sysbus = SYS_BUS_DEVICE(dev); > + for (int i = 0; i < platform_bus_num_irqs; i++) { > + int irq = platform_bus_base_irq + i; > + sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); > + } > + > + memory_region_add_subregion(sysmem, > + platform_bus_mem->base, > + sysbus_mmio_get_region(sysbus, 0)); > + > + return dev; > +} > diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build > index 0d82ceacc4..7aa3c1578d 100644 > --- a/hw/riscv/meson.build > +++ b/hw/riscv/meson.build > @@ -1,6 +1,7 @@ > riscv_ss = ss.source_set() > riscv_ss.add(files('aia.c')) > riscv_ss.add(files('boot.c')) > +riscv_ss.add(files('device-common.c')) > riscv_ss.add(files('fdt-common.c')) > riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) > riscv_ss.add(files('riscv_hart.c')) > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index ccea5784f0..a2671ae341 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -35,6 +35,7 @@ > #include "hw/riscv/riscv-iommu-bits.h" > #include "hw/riscv/virt.h" > #include "hw/riscv/boot.h" > +#include "hw/riscv/device-common.h" > #include "hw/riscv/fdt-common.h" > #include "hw/riscv/machines-qom.h" > #include "hw/riscv/numa.h" > @@ -683,31 +684,6 @@ static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, > memmap[VIRT_PLIC].size); > } > > -static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) > -{ > - DeviceState *dev; > - SysBusDevice *sysbus; > - int i; > - MemoryRegion *sysmem = get_system_memory(); > - > - dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); > - dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); > - qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); > - qdev_prop_set_uint32(dev, "mmio_size", s->memmap[VIRT_PLATFORM_BUS].size); > - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > - s->platform_bus_dev = dev; > - > - sysbus = SYS_BUS_DEVICE(dev); > - for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { > - int irq = VIRT_PLATFORM_BUS_IRQ + i; > - sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); > - } > - > - memory_region_add_subregion(sysmem, > - s->memmap[VIRT_PLATFORM_BUS].base, > - sysbus_mmio_get_region(sysbus, 0)); > -} > - > static void virt_build_smbios(RISCVVirtState *s) > { > MachineClass *mc = MACHINE_GET_CLASS(s); > @@ -1030,7 +1006,9 @@ static void virt_machine_init(MachineState *machine) > > gpex_pcie_init(system_memory, pcie_irqchip, s); > > - create_platform_bus(s, mmio_irqchip); > + s->platform_bus_dev = riscv_create_platform_bus(mmio_irqchip, > + &s->memmap[VIRT_PLATFORM_BUS], VIRT_PLATFORM_BUS_IRQ, > + VIRT_PLATFORM_BUS_NUM_IRQS); > > serial_mm_init(system_memory, s->memmap[VIRT_UART0].base, > 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, > diff --git a/include/hw/riscv/device-common.h b/include/hw/riscv/device-common.h > new file mode 100644 > index 0000000000..12af031bbf > --- /dev/null > +++ b/include/hw/riscv/device-common.h > @@ -0,0 +1,19 @@ > +/* > + * RISC-V board helpers for FDT generation. > + * > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef RISCV_DEVICE_COMMON_H > +#define RISCV_DEVICE_COMMON_H > + > +#include "exec/hwaddr.h" > +#include "hw/core/qdev.h" > + > +DeviceState *riscv_create_platform_bus(DeviceState *irqchip, > + const MemMapEntry *platform_bus_mem, > + int platform_bus_base_irq, > + int platform_bus_num_irqs); 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envelope-from=chao.liu@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Chao Liu From: Chao Liu via qemu development Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Aug 28, 2026 at 05:39:14PM +0800, Daniel Henrique Barboza wrote: > There will be code repetition instances added by the 'riscv-server-ref' > board w.r.t device creation and initialization. Instead of waiting for > that code to land we're adding helpers beforehand. The idea is to make > the new board code shorter and more palatable for reviewers. > > A new 'device-common' file is created for such helpers. We'll start > with the platform bus, a nice piece of software that only the 'virt' > board uses so far, and the 'riscv-server-ref' will use to support TPM > devices. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Chao Liu Thanks, Chao > --- > hw/riscv/device-common.c | 48 ++++++++++++++++++++++++++++++++ > hw/riscv/meson.build | 1 + > hw/riscv/virt.c | 30 +++----------------- > include/hw/riscv/device-common.h | 19 +++++++++++++ > 4 files changed, 72 insertions(+), 26 deletions(-) > create mode 100644 hw/riscv/device-common.c > create mode 100644 include/hw/riscv/device-common.h > > diff --git a/hw/riscv/device-common.c b/hw/riscv/device-common.c > new file mode 100644 > index 0000000000..d3c68a9e71 > --- /dev/null > +++ b/hw/riscv/device-common.c > @@ -0,0 +1,48 @@ > +/* > + * RISC-V board helpers for FDT generation. > + * > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > + > +#include "hw/riscv/device-common.h" > + > +#include "hw/core/platform-bus.h" > +#include "hw/core/qdev.h" > +#include "hw/core/qdev-properties.h" > +#include "hw/core/sysbus.h" > +#include "qapi/error.h" > +#include "system/address-spaces.h" > +#include "system/memory.h" > + > + > +DeviceState *riscv_create_platform_bus(DeviceState *irqchip, > + const MemMapEntry *platform_bus_mem, > + int platform_bus_base_irq, > + int platform_bus_num_irqs) > +{ > + MemoryRegion *sysmem = get_system_memory(); > + DeviceState *dev; > + SysBusDevice *sysbus; > + > + dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); > + dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); > + qdev_prop_set_uint32(dev, "num_irqs", platform_bus_num_irqs); > + qdev_prop_set_uint32(dev, "mmio_size", platform_bus_mem->size); > + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > + > + sysbus = SYS_BUS_DEVICE(dev); > + for (int i = 0; i < platform_bus_num_irqs; i++) { > + int irq = platform_bus_base_irq + i; > + sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); > + } > + > + memory_region_add_subregion(sysmem, > + platform_bus_mem->base, > + sysbus_mmio_get_region(sysbus, 0)); > + > + return dev; > +} > diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build > index 0d82ceacc4..7aa3c1578d 100644 > --- a/hw/riscv/meson.build > +++ b/hw/riscv/meson.build > @@ -1,6 +1,7 @@ > riscv_ss = ss.source_set() > riscv_ss.add(files('aia.c')) > riscv_ss.add(files('boot.c')) > +riscv_ss.add(files('device-common.c')) > riscv_ss.add(files('fdt-common.c')) > riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) > riscv_ss.add(files('riscv_hart.c')) > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index ccea5784f0..a2671ae341 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -35,6 +35,7 @@ > #include "hw/riscv/riscv-iommu-bits.h" > #include "hw/riscv/virt.h" > #include "hw/riscv/boot.h" > +#include "hw/riscv/device-common.h" > #include "hw/riscv/fdt-common.h" > #include "hw/riscv/machines-qom.h" > #include "hw/riscv/numa.h" > @@ -683,31 +684,6 @@ static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, > memmap[VIRT_PLIC].size); > } > > -static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) > -{ > - DeviceState *dev; > - SysBusDevice *sysbus; > - int i; > - MemoryRegion *sysmem = get_system_memory(); > - > - dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); > - dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); > - qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); > - qdev_prop_set_uint32(dev, "mmio_size", s->memmap[VIRT_PLATFORM_BUS].size); > - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > - s->platform_bus_dev = dev; > - > - sysbus = SYS_BUS_DEVICE(dev); > - for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { > - int irq = VIRT_PLATFORM_BUS_IRQ + i; > - sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); > - } > - > - memory_region_add_subregion(sysmem, > - s->memmap[VIRT_PLATFORM_BUS].base, > - sysbus_mmio_get_region(sysbus, 0)); > -} > - > static void virt_build_smbios(RISCVVirtState *s) > { > MachineClass *mc = MACHINE_GET_CLASS(s); > @@ -1030,7 +1006,9 @@ static void virt_machine_init(MachineState *machine) > > gpex_pcie_init(system_memory, pcie_irqchip, s); > > - create_platform_bus(s, mmio_irqchip); > + s->platform_bus_dev = riscv_create_platform_bus(mmio_irqchip, > + &s->memmap[VIRT_PLATFORM_BUS], VIRT_PLATFORM_BUS_IRQ, > + VIRT_PLATFORM_BUS_NUM_IRQS); > > serial_mm_init(system_memory, s->memmap[VIRT_UART0].base, > 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, > diff --git a/include/hw/riscv/device-common.h b/include/hw/riscv/device-common.h > new file mode 100644 > index 0000000000..12af031bbf > --- /dev/null > +++ b/include/hw/riscv/device-common.h > @@ -0,0 +1,19 @@ > +/* > + * RISC-V board helpers for FDT generation. > + * > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef RISCV_DEVICE_COMMON_H > +#define RISCV_DEVICE_COMMON_H > + > +#include "exec/hwaddr.h" > +#include "hw/core/qdev.h" > + > +DeviceState *riscv_create_platform_bus(DeviceState *irqchip, > + const MemMapEntry *platform_bus_mem, > + int platform_bus_base_irq, > + int platform_bus_num_irqs); > +#endif > -- > 2.43.0 >