From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Jia Wang <wangjia@ultrarisc.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>,
Pandith N <pandith.n@intel.com>,
Sia Jee Heng <jee.heng.sia@intel.com>,
dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
Frank Li <Frank.Li@nxp.com>
Subject: Re: [PATCH v2 4/4] dmaengine: dw-axi-dmac: Use bitfield helpers for registers
Date: Tue, 1 Sep 2026 10:02:09 +0300 [thread overview]
Message-ID: <apZ4cTZUHWruo828@ashevche-desk.local> (raw)
In-Reply-To: <20260901-dma-fix-v2-4-d7f0459ebb14@ultrarisc.com>
On Tue, Sep 01, 2026 at 02:16:07PM +0800, Jia Wang wrote:
> The driver open-codes several channel configuration and descriptor
> control bitfield writes with left shifts. Define masks for those fields
> and use FIELD_PREP() when programming the registers.
>
> Valid field values keep the same encoding. FIELD_PREP() confines values
> to their respective fields, but does not validate handshake numbers
> supplied through DMA specifiers.
...
> {
> u32 cfg_lo, cfg_hi;
>
> - cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
> - config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
> + cfg_lo = FIELD_PREP(CH_CFG_L_DST_MULTBLK_TYPE, config->dst_multblk_type) |
> + FIELD_PREP(CH_CFG_L_SRC_MULTBLK_TYPE, config->src_multblk_type);
Personally I would duplicate this to make each branch self-contained.
> if (chan->chip->dw->hdata->reg_map_8_channels &&
> !chan->chip->dw->hdata->use_cfg2) {
> - cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
> - config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
> - config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
> - config->src_per << CH_CFG_H_SRC_PER_POS |
> - config->dst_per << CH_CFG_H_DST_PER_POS |
> - config->prior << CH_CFG_H_PRIORITY_POS;
cfg_lo = FIELD_PREP(CH_CFG_L_DST_MULTBLK_TYPE, config->dst_multblk_type) |
FIELD_PREP(CH_CFG_L_SRC_MULTBLK_TYPE, config->src_multblk_type);
> + cfg_hi = FIELD_PREP(CH_CFG_H_TT_FC, config->tt_fc) |
> + FIELD_PREP(CH_CFG_H_HS_SEL_SRC, config->hs_sel_src) |
> + FIELD_PREP(CH_CFG_H_HS_SEL_DST, config->hs_sel_dst) |
> + FIELD_PREP(CH_CFG_H_SRC_PER, config->src_per) |
> + FIELD_PREP(CH_CFG_H_DST_PER, config->dst_per) |
> + FIELD_PREP(CH_CFG_H_PRIORITY, config->prior);
> } else {
> - cfg_lo |= config->src_per << CH_CFG2_L_SRC_PER_POS |
> - config->dst_per << CH_CFG2_L_DST_PER_POS;
> - cfg_hi = config->tt_fc << CH_CFG2_H_TT_FC_POS |
> - config->hs_sel_src << CH_CFG2_H_HS_SEL_SRC_POS |
> - config->hs_sel_dst << CH_CFG2_H_HS_SEL_DST_POS |
> - config->prior << CH_CFG2_H_PRIORITY_POS;
> + cfg_lo |= FIELD_PREP(CH_CFG2_L_SRC_PER, config->src_per) |
> + FIELD_PREP(CH_CFG2_L_DST_PER, config->dst_per);
cfg_lo = FIELD_PREP(CH_CFG_L_DST_MULTBLK_TYPE, config->dst_multblk_type) |
FIELD_PREP(CH_CFG_L_SRC_MULTBLK_TYPE, config->src_multblk_type) |
FIELD_PREP(CH_CFG2_L_SRC_PER, config->src_per) |
FIELD_PREP(CH_CFG2_L_DST_PER, config->dst_per);
> + cfg_hi = FIELD_PREP(CH_CFG2_H_TT_FC, config->tt_fc) |
> + FIELD_PREP(CH_CFG2_H_HS_SEL_SRC, config->hs_sel_src) |
> + FIELD_PREP(CH_CFG2_H_HS_SEL_DST, config->hs_sel_dst) |
> + FIELD_PREP(CH_CFG2_H_PRIORITY, config->prior);
> }
...
> - reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
> - DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS |
> - xfer_width << CH_CTL_L_DST_WIDTH_POS |
> - xfer_width << CH_CTL_L_SRC_WIDTH_POS |
> - DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
> - DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS);
> + reg = (FIELD_PREP(CH_CTL_L_DST_MSIZE, DWAXIDMAC_BURST_TRANS_LEN_4) |
> + FIELD_PREP(CH_CTL_L_SRC_MSIZE, DWAXIDMAC_BURST_TRANS_LEN_4) |
> + FIELD_PREP(CH_CTL_L_DST_WIDTH, xfer_width) |
> + FIELD_PREP(CH_CTL_L_SRC_WIDTH, xfer_width) |
> + FIELD_PREP(CH_CTL_L_DST_INC, DWAXIDMAC_CH_CTL_L_INC) |
> + FIELD_PREP(CH_CTL_L_SRC_INC, DWAXIDMAC_CH_CTL_L_INC));
Unneeded parentheses.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-09-01 7:02 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 6:16 [PATCH v2 0/4] dmaengine: dw-axi-dmac: Fix burst encoding, LLI dump and priority Jia Wang
2026-09-01 6:16 ` [PATCH v2 1/4] dmaengine: dw-axi-dmac: Fix AXI burst length encoding Jia Wang
2026-09-01 6:29 ` sashiko-bot
2026-09-01 6:16 ` [PATCH v2 2/4] dmaengine: dw-axi-dmac: Fix LLI dump out-of-bounds access Jia Wang
2026-09-01 6:29 ` sashiko-bot
2026-09-01 18:53 ` Frank Li
2026-09-01 6:16 ` [PATCH v2 3/4] dmaengine: dw-axi-dmac: Fix CH_CFG2 channel priority position Jia Wang
2026-09-01 6:28 ` sashiko-bot
2026-09-01 18:55 ` Frank Li
2026-09-01 6:16 ` [PATCH v2 4/4] dmaengine: dw-axi-dmac: Use bitfield helpers for registers Jia Wang
2026-09-01 7:02 ` Andy Shevchenko [this message]
2026-09-01 8:49 ` Jia Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=apZ4cTZUHWruo828@ashevche-desk.local \
--to=andriy.shevchenko@linux.intel.com \
--cc=Eugeniy.Paltsev@synopsys.com \
--cc=Frank.Li@kernel.org \
--cc=Frank.Li@nxp.com \
--cc=dmaengine@vger.kernel.org \
--cc=jee.heng.sia@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=pandith.n@intel.com \
--cc=vkoul@kernel.org \
--cc=wangjia@ultrarisc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.