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[35.189.192.250]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48442d787b8sm5393882f8f.29.2026.09.01.07.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 07:22:08 -0700 (PDT) Date: Tue, 1 Sep 2026 14:22:04 +0000 From: Mostafa Saleh To: Tao Tang Cc: Eric Auger , Peter Maydell , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Chao Liu , Jim MacArthur Subject: Re: [RFC v5 17/28] hw/arm/smmuv3: Add access checks for STRTAB_BASE and CR2 registers Message-ID: References: <20260813161515.2788900-1-tangtao1634@phytium.com.cn> <20260813162558.2808607-2-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260813162558.2808607-2-tangtao1634@phytium.com.cn> Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=smostafa@google.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Aug 14, 2026 at 12:25:55AM +0800, Tao Tang wrote: > Add access control for SMMU_STRTAB_BASE and SMMU_CR2 registers to > ensure they can only be modified when the SMMU is disabled. > > This implements: > - smmuv3_smmu_disabled_stable(): Check whether the SMMU is in a stable > disabled state (CR0.SMMUEN == 0 and CR0ACK.SMMUEN == 0); > - smmu_strtab_base_writable(): returns true only when IDR1.TABLES_PRESET==0 > and SMMU is completely disabled. > > Additionally, mask reserved bits on writes to SMMU_STRTAB_BASE using > SMMU_STRTAB_BASE_RESERVED. > > Fixes: fae4be38b35d ("hw/arm/smmuv3: Implement MMIO write operations") > Signed-off-by: Tao Tang > Reviewed-by: Pierrick Bouvier > --- > hw/arm/smmuv3.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 67 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 628911d3f21..de8ca7cda48 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -1484,6 +1484,36 @@ smmu_gerror_irq_cfg_writable(SMMUv3State *s, SMMUSecSID sec_sid) > return smmu_irq_cfg_writable(s, sec_sid, SMMU_IRQ_GERROR); > } > > +static inline int smmuv3_get_cr0ack_smmuen(SMMUv3State *s, SMMUSecSID sec_sid) > +{ > + /* > + * CR0, CR0ACK, S_CR0 and S_CR0ACK are bit-layout compatible, so we reuse > + * the CR0 field definitions and only switch banks via sec_sid to reduce > + * code duplication. Also the other bits in CR0/CR0ACK are relevant here. > + */ > + return FIELD_EX32(s->bank[sec_sid].cr0ack, CR0, SMMUEN); > +} > + > +/* Check if SMMU is disabled in stable status */ > +static inline bool smmuv3_smmu_disabled_stable(SMMUv3State *s, SMMUSecSID sec_sid) > +{ > + int cr0_smmuen = smmu_enabled(s, sec_sid); > + int cr0ack_smmuen = smmuv3_get_cr0ack_smmuen(s, sec_sid); > + return (cr0_smmuen == 0 && cr0ack_smmuen == 0); > +} > + > +/* Check if STRTAB_BASE register is writable */ > +static bool smmu_strtab_base_writable(SMMUv3State *s, SMMUSecSID sec_sid) > +{ > + /* SMMU_IDR1.TABLES_PRESET applies to both modeled interfaces. */ > + if (FIELD_EX32(s->bank[SMMU_SEC_SID_NS].idr[1], IDR1, TABLES_PRESET)) { > + return false; > + } > + Again, I think those are not configurable at the moment, so I'd drop such checks. > + /* Check SMMUEN conditions for the specific security domain */ > + return smmuv3_smmu_disabled_stable(s, sec_sid); > +} > + > static int smmuv3_cmdq_consume(SMMUv3State *s, Error **errp, SMMUSecSID sec_sid) > { > SMMUState *bs = ARM_SMMU(s); > @@ -1801,7 +1831,14 @@ static MemTxResult smmu_writell(SMMUv3State *s, hwaddr offset, > bank->gerror_irq_cfg0 = data & SMMU_GERROR_IRQ_CFG0_RESERVED; > return MEMTX_OK; > case A_STRTAB_BASE: > - bank->strtab_base = data; > + if (!smmu_strtab_base_writable(s, reg_sec_sid)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "STRTAB_BASE write ignored: register is RO\n"); > + return MEMTX_OK; > + } > + > + /* Clear reserved bits according to spec */ > + bank->strtab_base = data & SMMU_STRTAB_BASE_RESERVED; > return MEMTX_OK; > case A_CMDQ_BASE: > bank->cmdq.base = data; > @@ -1852,7 +1889,15 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, > bank->cr[1] = data; > break; > case A_CR2: > - bank->cr[2] = data; > + if (smmuv3_smmu_disabled_stable(s, reg_sec_sid)) { > + /* Allow write: SMMUEN is 0 in both CR0 and CR0ACK */ > + bank->cr[2] = data; > + } else { > + /* CONSTRAINED UNPREDICTABLE behavior: Ignore this write */ > + qemu_log_mask(LOG_GUEST_ERROR, > + "CR2 write ignored: register is read-only when " > + "CR0.SMMUEN or CR0ACK.SMMUEN is set\n"); > + } > break; > case A_IRQ_CTRL: > bank->irq_ctrl = data; > @@ -1915,12 +1960,32 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, > } > break; > case A_STRTAB_BASE: /* 64b */ > + if (!smmu_strtab_base_writable(s, reg_sec_sid)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "STRTAB_BASE write ignored: register is RO\n"); > + return MEMTX_OK; > + } > + > + data &= SMMU_STRTAB_BASE_RESERVED; > bank->strtab_base = deposit64(bank->strtab_base, 0, 32, data); > break; > case A_STRTAB_BASE + 4: > + if (!smmu_strtab_base_writable(s, reg_sec_sid)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "STRTAB_BASE + 4 write ignored: register is RO\n"); > + return MEMTX_OK; > + } > + > + data &= SMMU_STRTAB_BASE_RESERVED; SMMU_STRTAB_BASE_RESERVED is the mask for the whole stream table base it doesn't apply to A_STRTAB_BASE + 4 offset. Thanks, Mostafa > bank->strtab_base = deposit64(bank->strtab_base, 32, 32, data); > break; > case A_STRTAB_BASE_CFG: > + if (!smmu_strtab_base_writable(s, reg_sec_sid)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "STRTAB_BASE_CFG write ignored: register is RO\n"); > + return MEMTX_OK; > + } > + > bank->strtab_base_cfg = data; > if (FIELD_EX32(data, STRTAB_BASE_CFG, FMT) == 1) { > bank->sid_split = FIELD_EX32(data, STRTAB_BASE_CFG, SPLIT); > -- > 2.34.1 >