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From: Frank Li <Frank.li@oss.nxp.com>
To: Li Youhong <dayou5941@163.com>
Cc: Eugeniy.Paltsev@synopsys.com, vkoul@kernel.org,
	Frank.Li@kernel.org, dmaengine@vger.kernel.org,
	Li Youhong <liyouhong@kylinos.cn>, Frank Li <Frank.Li@nxp.com>
Subject: Re: [PATCH v2] dmaengine: dw-axi-dmac: convert to clk bulk APIs
Date: Tue, 1 Sep 2026 14:16:36 -0500	[thread overview]
Message-ID: <apcklCjTPr0sUWbm@SMW015318> (raw)
In-Reply-To: <20260901013916.194253-1-dayou5941@163.com>

On Tue, Sep 01, 2026 at 09:39:16AM +0800, Li Youhong wrote:
> From: Li Youhong <liyouhong@kylinos.cn>
>
> axi_dma_resume() enables cfgr_clk then core_clk. If enabling
> core_clk fails, return without disabling cfgr_clk, leaking the
> already-enabled clock.
>
> Switch both clocks to the clk bulk helpers so prepare/enable
> failures roll back automatically, and update probe/remove/
> suspend/resume accordingly.
>
> Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
> Suggested-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Li Youhong <liyouhong@kylinos.cn>
> ---
> v2:
> - Convert to clk bulk APIs
> - Use a static const clk table with ARRAY_SIZE/memcpy
>   v1: link: https://lore.kernel.org/all/20260831094438.2244538-1-dayou5941@163.com/
>
> ---
>  .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 23 ++++++-------------
>  drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  8 +++++--
>  2 files changed, 13 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index eebed2474210..3a957af0e089 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -1320,8 +1320,7 @@ static int axi_dma_suspend(struct axi_dma_chip *chip)
>  	axi_dma_irq_disable(chip);
>  	axi_dma_disable(chip);
>
> -	clk_disable_unprepare(chip->core_clk);
> -	clk_disable_unprepare(chip->cfgr_clk);
> +	clk_bulk_disable_unprepare(ARRAY_SIZE(chip->clks), chip->clks);
>
>  	return 0;
>  }
> @@ -1330,11 +1329,7 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
>  {
>  	int ret;
>
> -	ret = clk_prepare_enable(chip->cfgr_clk);
> -	if (ret < 0)
> -		return ret;
> -
> -	ret = clk_prepare_enable(chip->core_clk);
> +	ret = clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
>  	if (ret < 0)
>  		return ret;
>
> @@ -1524,13 +1519,10 @@ static int dw_probe(struct platform_device *pdev)
>
>  	chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
>
> -	chip->core_clk = devm_clk_get(chip->dev, "core-clk");
> -	if (IS_ERR(chip->core_clk))
> -		return PTR_ERR(chip->core_clk);
> -
> -	chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
> -	if (IS_ERR(chip->cfgr_clk))
> -		return PTR_ERR(chip->cfgr_clk);
> +	memcpy(chip->clks, dw_axi_dmac_clks, sizeof(chip->clks));
> +	ret = devm_clk_bulk_get(chip->dev, ARRAY_SIZE(chip->clks), chip->clks);
> +	if (ret)
> +		return ret;
>
>  	ret = parse_device_properties(chip);
>  	if (ret)
> @@ -1642,8 +1634,7 @@ static void dw_remove(struct platform_device *pdev)
>  	u32 i;
>
>  	/* Enable clk before accessing to registers */
> -	clk_prepare_enable(chip->cfgr_clk);
> -	clk_prepare_enable(chip->core_clk);
> +	clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
>  	axi_dma_irq_disable(chip);
>  	for (i = 0; i < dw->hdata->nr_channels; i++) {
>  		axi_chan_disable(&chip->dw->chan[i]);
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index 67cc199e24d1..fb11b525727e 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -22,6 +22,11 @@
>  #define DMAC_MAX_MASTERS	2
>  #define DMAC_MAX_BLK_SIZE	0x200000
>
> +static const struct clk_bulk_data dw_axi_dmac_clks[] = {
> +	{ .id = "cfgr-clk", },
> +	{ .id = "core-clk", },
> +};
> +

Avoid define varible in header file, in case header file included more
than once. I know you want to use marco ARRAY_SIZE().

#define DW_AXI_DMA_MAX_CLKS 2

chip->clks[0].id = "cfgr-clk";
chip->clks[1].id = "core-clk";

>  struct dw_axi_dma_hcfg {
>  	u32	nr_channels;
>  	u32	nr_masters;
> @@ -69,8 +74,7 @@ struct axi_dma_chip {
>  	int			irq[DMAC_MAX_CHANNELS];
>  	void __iomem		*regs;
>  	void __iomem		*apb_regs;
> -	struct clk		*core_clk;
> -	struct clk		*cfgr_clk;
> +	struct clk_bulk_data	clks[ARRAY_SIZE(dw_axi_dmac_clks)];
>  	struct dw_axi_dma	*dw;
>  };
>
> --
> 2.25.1
>

      parent reply	other threads:[~2026-09-01 19:16 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-01  1:39 [PATCH v2] dmaengine: dw-axi-dmac: convert to clk bulk APIs Li Youhong
2026-09-01  1:51 ` sashiko-bot
2026-09-01 19:16 ` Frank Li [this message]

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