Re: [PATCH 2/5] target/i386: Add LASS support in CR4

[Zhao Liu <zhao1.liu@intel.com>]

On Tue, Aug 25, 2026 at 08:57:31PM -0700, Kishen Maloor wrote:
> Date: Tue, 25 Aug 2026 20:57:31 -0700
> From: Kishen Maloor <kishen.maloor@intel.com>
> Subject: [PATCH 2/5] target/i386: Add LASS support in CR4
> X-Mailer: git-send-email 2.47.1
> 
> From: Isaku Yamahata <isaku.yamahata@intel.com>
> 
> CR4.LASS[bit 27] enables Linear Address Space Separation, and may be set
> only when CPUID.(EAX=7,ECX=1):EAX[6] enumerates LASS.
> 
> Recognize CR4.LASS as a valid bit by adding CR4_LASS_MASK to the known
> bits, i.e. clearing it from CR4_RESERVED_MASK. Mark it reserved in
> cr4_reserved_bits() and clear it in cpu_x86_update_cr4() when the guest
> CPUID does not enumerate LASS. This keeps CR4 handling consistent on
> paths that reach cpu_x86_update_cr4(), such as gdbstub register writes.
> 
> LASS is not emulated by TCG, so it is not added to TCG_7_1_EAX_FEATURES
> and cannot be set under TCG (helper_write_crN() and helper_vmrun() both
> reject reserved bits via cr4_reserved_bits()).
> 
> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
> [kishen: rewrote commit message, rebased, fixed formatting]
> Signed-off-by: Kishen Maloor <kishen.maloor@intel.com>
> ---
>  target/i386/cpu.h    | 7 ++++++-
>  target/i386/helper.c | 4 ++++
>  2 files changed, 10 insertions(+), 1 deletion(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>